ADT7320UCPZ-R2 datasheet(4/24 Pages) AD

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ADT7320

Preliminary Technical Data

Rev. PrA | Page 4 of 24

Shutdown Current

At 3.3 V

2.0

μA

Supply current in shutdown mode

At 5.5 V

4.4

μA

Supply current in shutdown mode

Power Dissipation Normal Mode

700

μW

VDD = 3.3 V, normal mode at 25°C

Power Dissipation 1 SPS

150

μW

Power dissipated for VDD = 3.3 V, TA = 25°C

1 Accuracy includes repeatability.

2 The equivalent three-sigma limits are ±0.15°C. This three-sigma specification is provided to enable comparison with other vendors who use these limits.

3 For higher accuracy at 5 V operation, contact an Analog Devices, Inc., sales representative.

4 Based on a floating average of 10 readings.

5 Drift includes solder heat resistance (SHR) and lifetime tests performed as per JEDEC Standard JESD22-A108.

SPI TIMING SPECIFICATIONS

TA = −40°C to +150°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns

(10% to 90% of VDD) and timed from a voltage level of 1.6 V.

Table 2.

Parameter1, 2

Limit at TMIN, TMAX (B Version)

Unit

Conditions/Comments

ns min

CS falling edge to SCLK active edge setup time3

100

ns min

SCLK high pulse width

100

ns min

SCLK low pulse width

ns min

Data valid to SCLK edge setup time

ns min

Data valid to SCLK edge hold time

ns min

SCLK active edge to data valid delay3

ns max

VDD = 4.5 V to 5.5 V

ns max

VDD = 2.7 V to 3.6 V

t74

ns min

Bus relinquish time after CS inactive edge

ns max

ns min

CS rising edge to SCLK edge hold time

ns min

CS falling edge to DOUT active time

ns max

VDD = 4.5 V to 5.5 V

ns max

VDD = 2.7 V to 3.6 V

t10

ns min

SCLK inactive edge to DOUT high

1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2 See Figure 2.

3 SCLK active edge is falling edge of SCLK.

4 This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading

capacitances.

SCLK

DIN

DOUT

MSB

LSB

MSB

LSB

t10

Figure 2. Detailed SPI Timing Diagram

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