MCP4902-ESLASHST datasheet(20/48 Pages) MICROCHIP

20 / 48 page

MCP4902/4912/4922

DS22250A-page 20

 2010 Microchip Technology Inc.

FIGURE 4-2:

Example for DNL Accuracy.

4.1.3

OFFSET ERROR

An offset error is the deviation from zero voltage output

when the digital input code is zero.

4.1.4

GAIN ERROR

A gain error is the deviation from the ideal output,

VREF– 1 LSb, excluding the effects of offset error.

4.2

Circuit Descriptions

4.2.1

OUTPUT AMPLIFIERS

The DAC’s outputs are buffered with a low-power,

precision CMOS amplifier. This amplifier provides low

offset voltage and low noise. The output stage enables

the device to operate with output voltages close to the

power supply rails. Refer to Section 1.0 “Electrical

Characteristics” for the analog output voltage range

and load conditions.

In addition to resistive load driving capability, the

amplifier will also drive high capacitive loads without

oscillation. The amplifier’s strong outputs allow VOUT to

be used as a programmable voltage reference in a

system.

Selecting a gain of 2 reduces the bandwidth of the

amplifier in Multiplying mode. Refer to Section 1.0

“Electrical Characteristics” for the Multiplying mode

bandwidth for given load conditions.

4.2.1.1

Programmable Gain Block

The rail-to-rail output amplifier has configurable gain,

allowing optimal full-scale outputs for different voltage

reference inputs. The output amplifier gain has two

selections, a gain of 1x (<GA> = 1) or a gain of 2x

(<GA> = 0).

The default value is a gain of 2 (<GA> = 0).

4.2.2

VOLTAGE REFERENCE

AMPLIFIERS

The input buffer amplifiers for the MCP4902/4912/4922

devices provide low offset voltage and low noise. A

Configuration bit for each DAC allows the VREF input to

bypass the VREF input buffer amplifiers, achieving a

Buffered or Unbuffered mode. Buffered mode provides

a very high input impedance, with only minor limitations

on the input range and frequency response.

Unbuffered (<BUF> = 0) is the default configuration.

Unbuffered mode provides a wide input range (0V to

VDD), with a typical input impedance of 165 k with

7pF.

4.2.3

POWER-ON RESET CIRCUIT

The internal Power-on Reset (POR) circuit monitors the

power supply voltage (VDD) during the device

operation. The circuit also ensures that the DACs

power-up with high output impedance (<SHDN> = 0,

typically 500 k

. The devices will continue to have a

high-impedance output until a valid write command is

performed to either of the DAC registers and the LDAC

pin meets the input low threshold.

If the power supply voltage is less than the POR

threshold (VPOR = 2.0V, typical), the DACs will be held

in their Reset state. The DACs will remain in that state

until VDD > VPOR and a subsequent write command is

received.

Figure 4-3 shows a typical power supply transient

pulse and the duration required to cause a reset to

occur, as well as the relationship between the duration

and trip voltage. A 0.1 µF decoupling capacitor,

mounted as close as possible to the VDD pin, can

provide additional transient immunity.

FIGURE 4-3:

Typical Transient Response.

111

110

101

100

011

010

001

000

Digital

Input

Code

Actual

transfer

function

Ideal transfer

function

Narrow code, < 1 LSb

DAC Output

Wide code, > 1 LSb

Transients

above

the

Transients below the

Time

Transient Duration

VPOR

VDD - VPOR

345

VDD – VPOR (V)

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