MCP4902-ESLASHST datasheet(27/48 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS22250A-page 27

MCP4902/4912/4922

6.0

TYPICAL APPLICATIONS

The MCP4902/4912/4922 family of devices are gen-

eral purpose DACs intended to be used in applications

where a precision with low-power and moderate

bandwidth is required.

Applications generally suited for the devices are:

• Set Point or Offset Trimming

• Sensor Calibration

• Digitally-Controlled Multiplier/Divider

• Portable Instrumentation (Battery Powered)

• Motor Control Feedback Loop

6.1

Digital Interface

The MCP4902/4912/4922 utilizes a 3-wire synchro-

nous serial protocol to transfer the DAC’s setup and

output values from the digital source. The serial proto-

col can be interfaced to SPI or Microwire peripherals

that is common on many microcontroller units (MCUs),

including Microchip’s PIC® MCUs and dsPIC® DSCs.

In addition to the three serial connections (CS, SCK

and SDI), the LDAC signal synchronizes the two DAC

outputs. By bringing down the LDAC pin to “low”, all

DAC input codes and settings in the two DAC input

registers are latched into their DAC output registers at

the same time. Therefore, both DACA and DACB

outputs are updated at the same time. Figure 6-1

shows an example of the pin connections. Note that the

LDAC pin can be tied low (VSS) to reduce the required

connections from 4 to 3 I/O pins. In this case, the DAC

output can be immediately updated when a valid

16-clock transmission has been received and CS pin

has been raised.

6.2

Power Supply Considerations

The typical application will require a bypass capacitor

in order to filter high-frequency noise. The noise can be

induced onto the power supply’s traces from various

events such as digital switching or as a result of

changes on the DAC’s output. The bypass capacitor

helps to minimize the effect of these noise sources.

Figure 6-1 illustrates an appropriate bypass strategy. In

this example, two bypass capacitors are used in

parallel: (a) 0.1 µF (ceramic) and (b) 10 µF (tantalum).

These capacitors should be placed as close to the

device power pin (VDD) as possible (within 4 mm).

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, VDD and

VSS should reside on the analog plane.

FIGURE 6-1:

Typical Connection

Diagram.

6.3

Layout Considerations

Inductively-coupled AC transients and digital switching

noises can degrade the input and output signal

integrity, and potentially reduce the device perfor-

mance. Careful board layout will minimize these effects

and increase the Signal-to-Noise Ratio (SNR). Bench

testing has shown that a multi-layer board utilizing a

low-inductance ground plane, isolated inputs and

isolated outputs with proper decoupling, is critical for

the best performance. Particularly harsh environments

may require shielding of critical signals.

Breadboards and wire-wrapped boards are not

recommended if low noise is desired.

VDD

AVSS

VSS

VREFA

VOUTA

VREFB

VOUTB

VREFA

VOUTA

VREFB

VOUTB

SDI

CS1

SDO

SCK

LDAC

CS0

C1 = 10 µF

C2 = 0.1 µF

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