IR3521 datasheet(3/45 Pages) IRF

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IR3521

Page 3

V3.03

PIN DESCRIPTION

PIN#

PIN SYMBOL

PIN DESCRIPTION

SVD

SVD (Serial VID Data) is a bidirectional signal that is an input and open drain output

for both master (AMD processor) and slave (IR3521), requires an external bias

voltage and should not be floated

PWROK

System wide Power Good signal and input to the IR3521. When asserted, the

IR3521 output voltage is programmed through the SVID interface protocol.

Connecting this pin to VCCL enables VFIX mode.

ENABLE

Enable input. A logic low applied to this pin puts the IC into fault mode. A logic high

on the pin enables the converter and causes the SVC and SVD input states to be

decoded and stored, determining the 2-bit Boot VID. Do not float this pin as the logic

state will be undefined.

IIN2

Output 2 average current input from the output 2 phase IC(s). This pin is also used

to communicate over voltage condition to the output 2 phase ICs.

SS/DEL2

Programs output 2 startup and over current protection delay timing. Connect an

external capacitor to LGND to program.

VDAC2

Output 2 reference voltage programmed by the SVID inputs and error amplifier non-

inverting input. Connect an external RC network to LGND to program dynamic VID

slew rate and provide compensation for the internal buffer amplifier.

OCSET2

Programs the output 2 constant converter output current limit and hiccup over-

current threshold through an external resistor tied to VDAC2 and an internal current

source from this pin. Over-current protection can be disabled by connecting a

resistor from this pin to VDAC2 to program the threshold higher than the possible

signal into the IIN2 pin from the phase ICs but no greater than 5V (do not float this

pin as improper operation will occur).

EAOUT2

Output of the output 2 error amplifier.

FB2

Inverting input to the Output 2 error amplifier.

VOUT2

Output 2 remote sense amplifier output.

VOSEN2+

Output 2 remote sense amplifier input. Connect to output at the load.

VOSEN2-

Output 2 remote sense amplifier input. Connect to ground at the load.

VOSEN1-

Output 1 remote sense amplifier input. Connect to ground at the load.

VOSEN1+

Output 1 remote sense amplifier input. Connect to output at the load.

VOUT1

Output 1 remote sense amplifier output.

FB1

Inverting input to the output 1 error amplifier. Converter output voltage can be

increased from the VDAC1 voltage with an external resistor connected between

VOUT1 and this pin (there is an internal current sink at this pin).

EAOUT1

Output of the output 1 error amplifier.

OCSET1

Programs the output 1 constant converter output current limit and hiccup over-

current threshold through an external resistor tied to VDAC1 and an internal current

source from this pin. Over-current protection can be disabled by connecting a

resistor from this pin to VDAC1 to program the threshold higher than the possible

signal into the IIN1 pin from the phase ICs but no greater than 5V (do not float this

pin as improper operation will occur).

VDAC1

Output 1 reference voltage programmed by the SVID inputs and error amplifier non-

inverting input. Connect an external RC network to LGND to program dynamic VID

slew rate and provide compensation for the internal buffer amplifier.

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