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IR3521 数据表(PDF) 7 Page - International Rectifier |
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IR3521 数据表(HTML) 7 Page - International Rectifier |
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7 / 45 page ![]() IR3521 Page 7 V3.03 PARAMETER TEST CONDITION MIN TYP MAX UNIT Soft Start and Delay Start Delay Measure Enable to EAOUTx activation 1 2.9 3.5 ms Start-up Time Measure Enable activation to PGOOD 3 8 13 ms OC Delay Time V(IINx) – V(OCSETx) = 500 mV 85 170 325 us SS/DELx to FBx Input Offset Voltage With FBx = 0V, adjust V(SS/DELx) until EAOUTx drives high 0.7 1.4 1.9 V Charge Current -30 -50 -70 A OC Delay/VID Off Discharge Currents Note 1 47 A Fault Discharge Current 2.5 4.5 6.5 A Hiccup Duty Cycle I(Fault) / I(Charge) 7 10 12 uA/uA Charge Voltage 3.5 3.9 4.2 V Delay Comparator Threshold Relative to Charge Voltage, SS/DELx rising Note 1 80 mV Delay Comparator Threshold Relative to Charge Voltage, SS/DELx falling Note 1 120 mV Delay Comparator Hysteresis Note 1 40 mV Discharge Comp. Threshold 150 200 300 mV Over-Current Comparators Input Offset Voltage 1V ≤ V(OCSETx) ≤ 3.3V -35 0 35 mV OCSET Bias Current -5% Vrosc(V)*100 0/Rosc(KΩ) +5% A 2048-4096 Count Threshold Adjust ROSC value to find threshold 16 kΩ 1024-2048 Count Threshold Adjust ROSC value to find threshold 20 kΩ Error Amplifiers VID ≥ 1V -0.5 0.5 % 0.8V ≤ VID < 1V -5 +5 mV System Set-Point Accuracy (Deviation from Table 1, 2, and 3 per test circuit in Figures 2A & 2B) 0.5V ≤ VID < 0.8V -8 +8 mV Input Offset Voltage Measure V(FBx) – V(VDACx)). Note 2 -1 0 1 mV FB1 Bias Current -5% Vrosc(V)*1000 /Rosc(KΩ) +5% A FB2 Bias Current -1 0 1 A DC Gain Note 1 100 110 135 dB Bandwidth Note 1 20 30 40 MHz Slew Rate Note 1 5.5 12 20 V/ s Sink Current 0.4 0.85 1 mA Source Current 5.0 8.5 12.0 mA Maximum Voltage Measure V(VCCL) – V(EAOUTx) 500 780 950 mV Minimum Voltage 120 250 mV Open Voltage Loop Detection Threshold Measure V(VCCL) - V(EAOUT), Relative to Error Amplifier maximum voltage. 125 300 600 mV Open Voltage Loop Detection Delay Measure PHSOUT pulse numbers from V(EAOUTx) = V(VCCL) to PGOOD = low. 8 Pulses Enable Input Blanking Time Noise Pulse < 100ns will not register an ENABLE state change. Note 1 75 250 400 ns VDAC References Source Currents Includes I(OCSETx) -8% 3050*Vrosc(V) / ROSC(kΩ) +8% A Sink Currents Includes I(OCSETx) -8% 2650*Vrosc(V) / ROSC(kΩ) +8% A PGOOD Output Under Voltage Threshold - Voutx Decreasing Reference to VDACx -365 -315 -265 mV |
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