IR3521

Page 11

V3.03

SYSTEM THEORY OF OPERATION

PWM Control Method

The PWM block diagram of the xPHASE3

with trailing edge modulation is used to provide system control. A voltage type error amplifier with high-gain and

wide-bandwidth, located in the Control IC, is used for the voltage control loop. The feed-forward control is

performed by the phase ICs as a result of sensing the input voltage (FET’s drain voltage). The PWM ramp slope

will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage

can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related

to changes in load current.

CLOCK GENERATOR

PWM

LATCH

CURRENT

SENSE

AMPLIFIER

R

S

SHARE ADJUST

ERROR AMPLIFIER

RESET

DOMINANT

ERROR

AMPLIFIER

COUT

IR35121CONTROL IC

IR3505 PHASE IC

Output 1 Only

PWM

COMPARATOR

PWM

COMPARATOR

-

+

+

+

RAMP

DISCHARGE

CLAMP

ENABLE

BODY

BRAKING

COMPARATOR

SHARE ADJUST

ERROR AMPLIFIER

RESET

DOMINANT

PWM

LATCH

CURRENT

SENSE

AMPLIFIER

R

S

IR3505 PHASE IC

CCS

REMOTE SENSE

AMPLIFIER

RCS

CFB2

CBST

RCS

CCS

CBST

CCP13

RDRP1

RFB12

RFB11

CDRP2

3K

CLK

D

Q

+

-

3K

RCP1

CCP14

CLK

D

Q

+

-

GND

VOUT1

VDAC1

VOUT1

ISHARE

PHSIN

VOSNS1-

VOSNS1+

DACIN

VCC

EAIN

GATEH

IIN1

VDRP1

LGND

EAOUT1

CLKOUT

CSIN-

CSIN+

GATEL

VCCL

VCCH

SW

VIN

FB1

CLKIN

PHSOUT

CLKIN

PHSOUT

PGND

EAIN

GATEH

ISHARE

PHSIN

DACIN

VCC

VCCL

VCCH

CSIN-

CSIN+

GATEL

PHSIN

PHSOUT

SW

PGND

VID6

IROSC

VID6

VID6

VID6

VID6

VID6

VID6

VID6

VID6

VID6

GATE DRIVE

VOLTAGE

-

+

+

+

ENABLE

RAMP

DISCHARGE

CLAMP

BODY

BRAKING

COMPARATOR

IFB1

VDRP1 AMP

VDAC

Figure 4 - PWM Block Diagram

Frequency and Phase Timing Control

The oscillator (system clock) is located in the Control IC and is programmable from 250 kHz to 9 MHZ by an

external resistor. The control IC clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase

timing of the phase ICs is controlled by the daisy chain loop. The control IC phase clock output (PHSOUT) is

connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to

PHSIN of the second phase IC, etc. The last phase IC (PHSOUT) is connected back to PHSIN of the control IC to

complete the loop. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins

and detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain

loop. Figure 5 shows the phase timing for a four phase converter.