TL16CP754C, TL16CM754C, TL16C754C

SLLS644E – DECEMBER 2007 – REVISED MAY 2010

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Transmit Holding Register (THR)

The transmitter section consists of the transmit holding register (THR) and the transmit shift register (TSR). The

transmit holding register is actually a 64-byte FIFO. The THR receives data and shifts it into the TSR where it is

converted to serial data and moved out on the TX terminal. If the FIFO is disabled, location zero of the FIFO is

used to store the byte. Characters are lost if overflow occurs.

FIFO Control Register (FCR)

This is a write-only register which is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and

receiver trigger levels, and selecting the type of DMA Signaling. Table 11 shows FIFO control register bit

settings.

Table 11. FIFO Control Register (FCR) Bit Settings

BIT NO.

BIT SETTINGS

0 = Disable the transmit and receive FIFOs

0

1 = Enable the transmit and receive FIFOs

0 = No change

1

1 = Clears the receive FIFO and resets it’s counter logic to zero. Will return to zero after clearing FIFO.

0 = No change

2

1 = Clears the transmit FIFO and resets it’s counter logic to zero. Will return to zero after clearing FIFO.

0 = DMA Mode 0

3

1 = DMA Mode 1

Sets the trigger level for the TX FIFO:

00 – 8 spaces

01 – 16 spaces

10 – 32 spaces

11 – 56 spaces

Sets the trigger level for the RX FIFO:

00 – 1 characters

7:6

01 – 4 characters

10 – 56 characters

11 – 60 characters

(1)

FCR[5

−4] can be modified and enabled only when EFR[4] is set. This is because the transmit trigger level is regarded as an enhanced

function.

Line Control Register (LCR)

This register controls the data communication format. The word length, number of stop bits, and parity type are

selected by writing the appropriate bits to the LCR. Table 12 shows line control register bit settings.

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