TL16CP754CPMRG4 datasheet(37/49 Pages) TI

37 / 49 page

TL16CP754C, TL16CM754C, TL16C754C

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SLLS644E – DECEMBER 2007 – REVISED MAY 2010

Divisor Latches (DLL, DLH)

Two 8-bit registers store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH,

stores the most significant part of the divisor. DLL stores the least significant part of the division.

DLL and DLH can only be written to before sleep mode is enabled (i.e., before IER[4] is set).

Transmission Control Register (TCR)

This 8-bit register is used to store the receive FIFO threshold levels to start/stop transmission during

hardware/software flow control. Table 20 shows transmission control register bit settings.

Table 20. Transmission Control Register (TCR) Bit

Settings

BIT NO.

BIT SETTINGS

3:0

RCV FIFO trigger level to HALT transmission (0–60)

7:4

RCV FIFO trigger level to RESTORE transmission (0–60)

TCR trigger levels are available from 0–60 bytes with a granularity of four.

TCR can be written to only when EFR[4] = 1 and MCR[6] = 1. The programmer must program the TCR such that

TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must

be programmed with this condition before Auto-RTS or software flow control is enabled to avoid spurious

operation of the device.

Trigger Level Register (TLR)

This 8-bit register is used to store the transmit and received FIFO trigger levels used for DMA and interrupt

generation. Trigger levels from 4

−60 can be programmed with a granularity of 4. Table 21 shows trigger level

Table 21. Trigger Level Register (TLR) Bit Settings

BIT NO.

BIT SETTINGS

Transmit FIFO trigger levels (4–60), number of spaces

3:0

available

RCV FIFO trigger levels (4–60), number of characters

7:4

available

TLR can be written to only when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are zero, then the

selectable trigger levels via the FIFO control register (FCR) are used for the transmit and receive FIFO trigger

levels. Trigger levels from 4–60 bytes are available with a granularity of four. The TLR should be programmed for

N/4, where N is the desired trigger level.

FIFO Ready Register

The FIFO ready register provides real-time status of the transmit and receive FIFOs. Table 22 shows the FIFO

ready register bit settings.

Table 22. FIFO Ready Register

BIT NO.

BIT SETTINGS

0 = There are less than a TX trigger level number of spaces available in the TX FIFO.

3:0

1 = There are at least a TX trigger level number of spaces available in the TX FIFO

0 = There are less than a RX trigger level number of characters in the RX FIFO.

7:4

1 = The RX FIFO has more than a RX trigger level number of characters available for reading OR a timeout condition

has occurred.

The FIFORdy register is a read only register and can be accessed when any of the four UARTs are selected CS

A–D = 0, MCR[2] (FIFORdy Enable) is a 1 and loopback is disabled. Its address space is 111.

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