TL16CP754C, TL16CM754C, TL16C754C

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SLLS644E – DECEMBER 2007 – REVISED MAY 2010

Table 12. Line Control Register (LCR) Bit Settings

BIT NO.

BIT SETTINGS

Specifies the word length to be transmitted or received.

00 – 5 bits

1:0

01 – 6 bits

10

− 7 bits

11 – 8 bits

Specifies the number of stop bits:

0 – 1 stop bits (Word length = 5, 6, 7, 8)

2

1 – 1.5 stop bits (Word length = 5)

1 – 2 stop bits (Word length = 6, 7, 8) 3

0 = No parity

3

1 = A parity bit is generated during transmission and the receiver checks for received parity.

0 = Odd parity is generated (if LCR[3] = 1)

4

1 = Even parity is generated (if LCR[3] = 1)

Selects the forced parity format (if LCR(3) = 1)

5

If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data.

If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received data.

Break control bit.

6

0 = Normal operating condition

1 = Forces the transmitter output to go low to alert the communication terminal.

0 = Normal operating condition

7

1 = Divisor latch enable

Line Status Register (LSR)

Table 13 shows line status register bit settings.

Table 13. Line Status Register (LSR) Bit Settings

BIT NO.

BIT SETTINGS

0 = No data in the receive FIFO

0

1 = At least one character in the RX FIFO

0 = No overrun error

1

1 = Overrun error has occurred.

0 = No parity error in data being read from RX FIFO

2

1 = Parity error in data being read from RX FIFO

0 = No framing error in data being read from RX FIFO

3

1 = Framing error occurred in data being read from RX FIFO (i.e., received data did not have a valid stop bit)

0 = No break condition

4

1 = A break condition occurred and associated byte is 00. (i.e., RX was low for at least one character time frame).

0 = Transmit hold register is NOT empty

5

1 = Transmit hold register is empty. The processor can now load up to 64 bytes of data into the THR if the TX FIFO is

enabled.

0 = Transmitter hold AND shift registers are not empty.

6

1 = Transmitter hold AND shift registers are empty.

0 = Normal operation

7

1 = At least one parity error, framing error or break indication are stored in the receiver FIFO. Bit 7 is cleared when no

errors are present in the FIFO.

When the LSR is read, LSR[4:2] reflects the error bits [BI, FE, PE] of the character at the top of the RX FIFO

(next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is

output directly onto the output data-bus, DI[4:2], when the LSR is read. Therefore, errors in a character are

identified by reading the LSR and then reading the RHR.

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