ADP4100 datasheet(13/22 Pages) ONSEMI

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ADP4100

http://onsemi.com

Figure 9. Overcurrent Latchoff Waveforms

Channel 1: CSREF, Channel 2: COMP,

Channel 3: PWM1

An inherent per phase current limit protects individual

phases if one or more phases stops functioning because of a

faulty component. This limit is based on the maximum

normal mode COMP voltage.

Output Current Monitor

IMON is an analog output from the ADP4100

representing the total current being delivered to the load. It

outputs an accurate current that is directly proportional to

the current set by the ILIMFS resistor.

(eq. 7)

IIMON + 10 ISW ILIMFS

The current is then run through a parallel RC connected

from the IMON pin to the FBRTN pin to generate an

accurately scaled and filtered voltage as per the VR11.1

specification. The size of the resistor is used to set the IMON

scaling.

The scaling is set such that IMON = 900 mV at the TDC

current of the processor. This means that the RIMON

resistor should be chosen as follows.

From the Current−Limit Setpoint paragraph we know the

following:

(eq. 8)

IILIMFS +

1mW

ILOAD

RLIMFS

IIMON + 10

1mW

ILOAD

RLIMFS

For a 150 A current limit RLIMFS = 6.81 kW. Assuming the

TDC = 135 A then VMON should equal 900 mV when

ILOAD = 135 A.

When ILOAD = 135 A, IMON equals:

(eq. 9)

IMON + 10

1mW

135 A

6.81 kW

+ 198mA

VIMON + 900 mV + 198 mA RMON

This gives a value of 4.54 k

W for RMON.

If the TDC and OCP limit for the processor have to be

changed then it may be necessary to change the ILIMITFS

resistor only. This is because the ILIMITFS resistor sets up

both the current limit and also the current out of the IMON

pin, as explained earlier.

The IMON pin also includes an active clamp to limit the

IMON voltage to 1.15 V MAX while maintaining accuracy

at 900 mV full scale.

Active Impedance Control Mode

For controlling the dynamic output voltage droop as a

function of output current, the CSA gain and load line

programming can be scaled to be equal to the droop

impedance of the regulator times the output current. This

droop voltage is then used to set the input control voltage to

the system. The droop voltage is subtracted from the DAC

reference input voltage directly to tell the error amplifier

where the output voltage should be. This allows enhanced

feed−forward response.

Load Line Setting

For load line values greater than 1 m

W, RCSA can be set

equal to RO, and the LLSET pin can be directly connected

to the CSCOMP pin. When the load line value needs to be

less than 1 m

W, two additional resistors are required.

Figure 10 shows the placement of these resistors.

Figure 10. Load Line Setting Resistors

CSSUM

CSCOMP

CSREF

ADP4100

LLSET

QLL

OPTIONAL LOAD LINE

SELECT SWITCH

RLL2

RLL1

The two resistors RLL1 and RLL2 set up a divider between

the CSCOMP pin and CSREF pin. This resistor divider is

input into the LLSET pin to set the load line slope RO of the

VR according to the following equation:

(eq. 10)

RO +

RLL2

RLL1 ) RLL2

RCSA

The resistor values for RLL1 and RLL2 are limited by two

factors.

• The minimum value is based upon the loading of the

CSCOMP pin. This pin’s drive capability is 500

and the majority of this should be allocated to the CSA

feedback. If the current through RLL1 and RLL2 is limited

to 10% of this (50

mA), the following limit can be placed

for the minimum value for RLL1 and RLL2:

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