ADP4100

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17

The maximum power dissipated is calculated using

Equation 21.

(eq. 21)

2

where:

(if the 12 V input supply is 12 V

the 12 V input supply is 12 V

This is specified as 4.7 V.

The CECC standard specification for power rating in

surface−mount resistors is: 0603 = 0.1 W, 0805 = 0.125 W,

1206 = 0.25 W.

VCC3

The ADP4100 has an internal 3.3 V LDO to supply the

internal circuits on the ADP4100. A 1

mF X7R capacitor

should be placed between this pin and AGND. This should

not be loaded by an external circuitry.

Driver Connections

Each driver in the external circuit is connected to one

PWM signal from the controller. The PWM signal controls

when the driver turns on and off both the high and low side

FET’s.

Each driver is also connected to either the OD1 or ODN

signal from the controller. This signal is used to disable the

driver, i.e. both high side and low side FET’s are disabled.

Drivers are disabled when OD pins are low and switching

when the OD pin is high. Phases which are enabled during

PSI should be connected to OD1. Phases which are disabled

during PSI should be connected to ODN. Extreme care

should be taken to ensure that the controller configuration

(set by the PSI_Set pin) matches the OD1 and ODN

connections on the board.

VID Inputs

The ADP4100 has seven VID Input pins which are used

to set the target output voltage. The VID codes are decoded

using the following VR11.1 Table. An input voltage of less

than 0.3 V is decoded as logic low. An input voltage of

greater than 0.8 V is decoded as logic high. If the pins are left

open then an internal pulldown will pull the pin low.