ADP4100 datasheet(14/22 Pages) ONSEMI

14 / 22 page

ADP4100

http://onsemi.com

(eq. 11)

RLL1 ) RLL2 w

ILIM RCSA

10*6

Here, ILIM is the current−limit current, which is the

maximum signal level that the CSA responds to.

• The maximum value is based upon minimizing induced

dc offset errors based on the bias current of the LLSET

pin. To keep the induced dc error less than 1 mV, which

makes this error statistically negligible, place the

following limit of the parallel combination of RLL1

and RLL2:

It is best to select the resistor values to minimize their

values to reduce the noise and parasitic susceptibility of the

feedback path.

(eq. 12)

RLL1 RLL2

RLL1 ) RLL2

v 1

10*3

120

10*9 +

8.33 kW

By combining Equation 10 with Equation 12 and selecting

minimum values for the resistors, the following equations

result:

(eq. 13)

RLL2 +

ILIM RO

50 mA

(eq. 14)

RLL1 +

RCSA

* 1

RLL2

Therefore, both RLL1 and RLL2 need to be in parallel and

less than 8.33 k

Another useful feature for some VR applications is the

ability to select different load lines. Figure 10 shows an

optional MOSFET switch that allows this feature. Here,

design for RCSA = RO(MAX) (selected with QLL on) and then

use Equation 10 to set RO = RO(MIN) (selected with QLL off).

For this design, RCSA = RO = 1 mW. As a result, connect

LLSET directly to CSCOMP; the RLL1.

Current Control Mode and Thermal Balance

The ADP4100 has individual inputs (SW1 to SW6) for

each phase that are used for monitoring the current of each

phase. This information is combined with an internal ramp

to create a current balancing feedback system that has been

optimized for initial current balance accuracy and dynamic

thermal balancing during operation. This current balance

information is independent of the average output current

information used for positioning.

The magnitude of the internal ramp can be set to optimize

the transient response of the system. It also monitors the

supply voltage for feed−forward control for changes in the

supply. A resistor connected from the power input voltage

to the RAMPADJ pin determines the slope of the internal

PWM ramp.

Voltage Control Mode

A high gain, high bandwidth, voltage mode error

amplifier is used for the voltage mode control loop. The

control input voltage to the positive input is set via the VID

logic according to the voltages listed in VID Code Table.

The VID code is set using the VID Input pins.

This voltage is also offset by the droop voltage for active

positioning of the output voltage as a function of current,

commonly known as active voltage positioning. The output

of the amplifier is the COMP pin, which sets the termination

voltage for the internal PWM ramps.

The negative input (FB) is tied to the output sense location

with Resistor RB and is used for sensing and controlling the

output voltage at this point. A current source (equal to

mA) from the FB pin flowing through RB is used for

setting the no load offset voltage from the VID voltage. The

no load voltage is negative with respect to the VID DAC for

Intel CPU’s.

The value of RB can be found using the following

equation:

(eq. 15)

RB +

VVID * VONL

IFB

RAMPADJ Input Current

The resistor connected to the Rampadj pin sets the internal

PWM ramp. The value for this resistor is chosen to provide

the combination of thermal balance, stability and transient

response.

(eq. 16)

RR +

AR L

AD RDS CR

Where

AR is the internal ramp amplifier gain (= 0.5)

AD is the current balancing amplifier gain (= 5)

RDS is the total low side MOSFET on resistance

CR is the internal ramp capacitor value (= 5pF).

The internal ramp voltage can be calculated as follows:

(eq. 17)

VR +

AR (1 * D) VVID

RR CR fSW

The size of the internal ramp can be made larger or

smaller. If it is made larger, stability and noise rejection

improves but the transient performance decreases. If the

ramp is made smaller then the transient response improves

however noise rejection and stability degrades.

COMP Pin Ramp

There is a ramp signal on the COMP signal, which is due

to the droop voltage and the output voltage ramps. This ramp

adds to the internal ramp to produce the following ramp

signal at the PWM input.

(eq. 18)

VRT +

1 *

2 (1*n D)

n fSW CX RO

Where Cx = bulk capacitance

RO = Droop

n = number of phases

fSW = switching frequency per phase

D = duty cycle

VR = Internal Ramp Voltage (calculated in

Rampadj section of this data sheet)

ADP4100 数据表(PDF) 14 Page - ON Semiconductor

ADP4100 数据表(HTML) 14 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

数据表下载