ADP4100

http://onsemi.com

16

PSI Set Table

# of Phases

Normally

PSI Set

Phases on During

PSI

6

High

Low

Phase 1 and 4

Phase 1

5

High

Low

Phase 1 and 4

Phase 1

4

High

Low

Phase 1 and 3

Phase 1

3

High

Low

Phase 1

Phase 1

2

High

Low

Phase 1

Phase 1

1

High

Low

Phase 1

Phase 1

Output Crowbar

As part of the protection for the load and output

components of the supply, the PWM outputs are driven low

(turning on the low−side MOSFETs) when the output

voltage exceeds the upper crowbar threshold. This crowbar

action stops once the output voltage falls below the release

threshold of approximately 300 mV.

The value for the crowbar limit follows the PWRGD high

limit.

Turning on the low−side MOSFETs pulls down the output

as the reverse current builds up in the inductors. If the output

overvoltage is due to a short in the high−side MOSFET, this

action current−limits the input supply or blows its fuse,

protecting the microprocessor from being destroyed.

Output Enable and UVLO

For the ADP4100 to begin switching, the input supply

current to the controller must be higher than the UVLO

threshold and the EN pin must be higher than its 0.8 V

threshold. This initiates a system startup sequence. If either

UVLO or EN is less than their respective thresholds, the

ADP4100 is disabled. This holds the PWM outputs at

ground and forces PWRGD, ODN and OD1 signals low.

In the application circuit (see Figure 2), the OD1 pin

should be connected to the OD inputs of the external drivers

for the phases that are always on. The ODN pin should be

connected to the OD inputs of the external drivers on the

phases that are shutdown during low power operation.

Grounding the driver OD inputs disables the drivers such

that both DRVH and DRVL are grounded. This feature is

important in preventing the discharge of the output

capacitors when the controller is shut off. If the driver

outputs are not disabled, a negative voltage can be generated

during output due to the high current discharge of the output

capacitors through the inductors.

Thermal Monitoring

The ADP4100 includes a thermal monitoring channel

using a thermistor.

The VR thermal monitoring circuits require an NTC

thermistor to be placed from TTSENSE to GND. For best

accuracy, the thermistors can be linearized using resistors. A

sourced out of the TTSENSE pin into the thermistor. The

resulting voltage is compared with the VRHOT Threshold

(0.81 V). When the meaured voltage goes below the

threshold (i.e. using this thermistor and resistor

combination, when the temperature has exceeded

approximately 85

°C) the VRHOT signal asserts high.

VRHOT is low when the temperature is below the limit (i.e.

the volatge is higher than the threshold).

Figure 11. TTSENSE Diagram

NTC

100 kW

20 kW

TTSENSE

VRHOT

0.81 V

+

-

120 mA

Shunt Resistor

The ADP4100 uses a shunt to generate 5.0 V from the

12 V supply range. A trade−off can be made between the

power dissipated in the shunt resistor and the UVLO

threshold. Figure 12 shows the typical resistor value needed

to realize certain UVLO voltages. It also gives the maximum

power dissipated in the shunt resistor for these UVLO

voltages.

Figure 12. Typical Shunt Resistor Value and Power

Dissipation for Different UVLO Voltage

Rshunt

Pshunt

2−0603 Limit

2−0805 Limit

400

350

200

150

10

11

14

15

300

250

8

9

12

13

16

0.325

ICC (UVLO)

0.3

0.275

0.25

0.225

0.2

0.175