STM6513

Block diagram

Doc ID 16490 Rev 2

11/29

STM6513 hookup with RST1 and RST2, bridging the PS_hold reset pulse during the

microprocessor reset initiated by the STM6513 Smart Reset device:

Figure 4.

Typical application diagram

Figure 5.

Timing waveforms

AM00375a

VCC

PMU

Seq.

logic

LD00

...

LD07

PWR

SW

POWER

KEY

RST_n

PS_hold

VREG

STM6513

TSR

TRECADJ

RST1 (PP)

RST2 (OD)

SR0

SR1

VREG

(PU resistor)

MCU

RST

PS_hold

GPIO1

GPIOn

KEYn

KEY1

Forces PS_hold

high during

reset period

CtREC

100 k

Ω

Factory -

programmed

tREC2

tREC1

tREC1

tSRC

tREC2

AM00376V2

POR initiated

SR0, SR1

RST2 (OD)

RST1 (PP)

by CtREC

(210 ms)

(~1 s)

(~1 s)

Smart Reset™ initiated

(210 ms)