STM6513 datasheet(5/29 Pages) STMICROELECTRONICS

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STM6513

Description

Doc ID 16490 Rev 2

5/29

Description

The STM6513 has two separate delayed Smart Reset inputs (SR0, SR1) which when taken

low simultaneously provide three user-selectable delayed Smart Reset setup time (tSRC)

options of 2 s, 6 s and 10 s. These are selected through a three-state TSR input pin: when

connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to VCC,

tSRC = 10 s (all the times are minimum). There are two reset outputs, both going active

simultaneously after both the Smart Reset inputs were held active for the selected tSRC

delay time. The first reset output, RST1, is active-high, push-pull; the second reset output,

RST2, is active-low, open-drain requiring an external pull-up resistor. The duration of the

output reset pulses is independently programmable: tREC1 is user-programmable (by

external capacitor CtREC), tREC2 is factory-programmed to 210 ms (typ.), with the option of

360 ms typ. Additionally, the VCC is monitored and if it drops below the selected VRST

threshold, both the reset outputs go active and remain so while VCC is below the VRST

threshold, plus the defined duration of the reset pulse tREC on each output.

Smart Reset devices

The Smart Reset device family STM65xx provides a useful feature that ensures inadvertent

short reset push-button closures do not cause system resets. This is done by implementing

extended Smart Reset input delay (tSRC). Once the valid Smart Reset input levels and setup

delay are met, the device generates an output reset pulse with user-programmable timeout

period (tREC).

The Smart Reset inputs can be also connected to the applications interrupt to allow the

control of both the interrupt pin and the hard reset functions. If the push-buttons are closed

for a short time, the processor is only interrupted. If the system still does not respond

properly, holding the push-buttons for the extended setup time (tSRC) causes hard reset of

the processor through the reset outputs. The Smart Reset feature helps significantly

increase system stability.

The STM65xx family of Smart Reset devices consists of low current microprocessor reset

circuits targeted at applications such as MP3 players, navigation, smartphones or mobile

phones; generally any application that requires delayed reset push-button(s) response for

improved system stability. The STM65xx devices feature single or dual Smart Reset inputs

(SR). The delayed Smart Reset setup time (tSRC) options of 2 s, 6 s and 10 s

(all min.) are adjustable by an external capacitor on the SRC pin or selectable by three-state

logic. The delayed setup period ignores switch closures shorter than tSRC, thus preventing

unwanted resets.

The STM65xx devices have active-low (optionally active-high) open-drain reset (RST)

output(s) with or without internal pull-up resistor or push-pull as output options, with factory-

programmed or capacitor-adjustable or push-buttons defined output reset pulse duration,

with or without power-on reset function.

Some devices also have an undervoltage monitoring feature: the reset output is also

asserted when the monitored supply voltage VCC drops below the specified threshold. The

reset output remains asserted for the reset timeout period (tREC) after the monitored supply

voltage goes above the specified threshold.

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