AD7441BRTZ-R2 datasheet(18/24 Pages) AD

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AD7441/AD7451

Rev. D | Page 18 of 24

MODES OF OPERATION

The operating mode of the AD7441/AD7451 is selected by

controlling the logic state of the CS signal during a conversion.

There are two operating modes: normal mode and power-down

mode. The point at which CS is pulled high after the conversion

is initiated determines whether the part enters power-down mode.

Similarly, if already in power-down, CS controls whether the

device returns to normal operation or remains in power-down.

These modes provide flexible power management options that

can optimize the power dissipation/throughput rate ratio for

differing application requirements.

NORMAL MODE

This mode is intended for fastest throughput rate performance.

The user does not have to worry about any power-up times with

the AD7441/AD7451 remaining fully powered up all the time.

Figure 29 shows the general diagram of the operation of the

AD7441/AD7451 in this mode. The conversion is initiated

on the falling edge of CS (see the

section). To

ensure that the part remains fully powered up,

Serial Interface

CS must remain

low until at least 10 SCLK falling edges elapse after the falling

edge of CS.

If CS is brought high any time after the 10th SCLK falling edge,

but before the 16th SCLK falling edge, the part remains pow-

ered up, however the conversion is terminated and SDATA goes

back into three-state. Sixteen serial clock cycles are required to

complete the conversion and access the complete conversion

result. CS can idle high until the next conversion or can idle

low until sometime prior to the next conversion. Once a data

transfer is complete—that is, when SDATA has returned to

three-state—another conversion can be initiated after the

quiet time, tQUIET, elapses again bringing CS low.

110

SCLK

SDATA

4 LEADING ZEROS + CONVERSION RESULT

Figure 29. Normal Mode Operation

POWER-DOWN MODE

This mode is intended for use in applications where slower

throughput rates are required; either the ADC is powered

down between each conversion or a series of conversions can

be performed at a high throughput rate and the ADC is then

powered down for a relatively long duration between these

bursts of conversions. When the AD7441/AD7451 are in

power-down mode, all analog circuitry is powered down.

For the AD7441/AD7451 to enter power-down mode, the

conversion process must be interrupted by bringing CS high

anywhere after the second falling edge of SCLK and before

the 10th falling edge of SCLK, as shown in

Figure 30

Once CS has been brought high in this window of SCLKs, the

part enters power-down, the conversion that was initiated by

the falling edge of CS is terminated, and SDATA goes back into

three-state. The time from the rising edge of CS to SDATA

three-state enabled is never greater than t8 (see the

section). If

Timing

Specifications

CS is brought high before the second

SCLK falling edge, the part remains in normal mode and does

not power down. This avoids accidental power-down due to

glitches on the CS line.

To exit power-down mode and power up the AD7441/AD7451

again, a dummy conversion is performed. On the falling edge

of CS, the device begins to power up and continues to do so

as long as CS is held low until after the falling edge of the 10th

SCLK. The device is fully powered up after 1 μs has elapsed and,

as shown in

, valid data results from the next

conversion.

Figure 31

SCLK

SDATA

THREE-STATE

Figure 30. Entering Power-Down Mode

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