AD7441/AD7451

Rev. D | Page 20 of 24

POWER VS. THROUGHPUT RATE

By using the power-down mode on the device when not con-

verting, the average power consumption of the ADC decreases

at lower throughput rates. Figure 32 shows how, as the through-

put rate is reduced, the device remains in its power-down state

longer and the average power consumption reduces accordingly.

For example, if the AD7441/AD7451 are operated in continuous

sampling mode with a throughput rate of 100 kSPS and an SCLK

of 18 MHz, and the device is placed in the power-down mode

between conversions, then the power consumption during

If the power-up time is one dummy cycle (1 μs) and the remain-

ing conversion time is another cycle (1 μs), then the AD7441/

AD7451 can be said to dissipate 9.25 mW for 2 μs during each

conversion cycle. (This power consumption figure assumes a

very short time to enter power-down mode. This power figure

increases as the burst of clocks used to enter power-down mode

is increased). The AD7441/AD7451 consume just 5 μW for the

remaining 8 μs.

Calculate the power numbers in Figure 32 as follows:

If the throughput rate = 100 kSPS, then the cycle time = 10 μs,

and the average power dissipated during each cycle is

(2/10) × 9.25 mW = 1.85 mW

during normal operation is 4 mW maximum.

The AD7441/AD7451 can now be said to dissipate 4 mW for

2 μs during each conversion cycle.

The average power dissipated during each cycle with a

throughput rate of 100 kSPS is, therefore,

(2/10) × 4 mW = 0.8 mW

THROUGHPUT (kSPS)

100

0350

0.01

50

100

150

200

250

300

0.1

1

10

Figure 32. Power vs. Throughput Rate for Power-Down Mode

For optimum power performance in throughput rates above

320 kSPS, it is recommended that the serial clock frequency be

reduced.

MICROPROCESSOR AND DSP INTERFACING

The serial interface on the AD7441/AD7451 allows the part to

be connected directly to a range of different microprocessors.

This section explains how to interface the AD7441/AD7451

with some of the more common microcontroller and DSP serial

interface protocols.

AD7441/AD7451 to ADSP-21xx

The ADSP-21xx family of DSPs is interfaced directly to the

AD7441/AD7451 without any glue logic required. The SPORT

control register is set up as follows:

TFSW = RFSW = 1

Alternate framing

INVRFS = INVTFS = 1

Active low frame signal

DTYPE = 00

Right justify data

SLEN = 1111

16-bit data-words

ISCLK = 1

Internal serial clock

TFSR = RFSR = 1

Frame every word

IRFS = 0

ITFS = 1

To implement power-down mode, SLEN is set to 1001 to issue

an 8-bit SCLK burst.

The connection diagram is shown in Figure 33. ADSP-21xx has

the TFS and RFS of the SPORT tied together, with TFS set as an

output and RFS set as an input. The DSP operates in alternate

framing mode, and the SPORT control register is set up as

described. The frame synchronization signal generated on the

TFS is tied to CS, and, as with all signal processing applications,

equidistant sampling is necessary. However, in this example,

the timer interrupt is used to control the sampling rate of the

ADC, and, under certain conditions, equidistant sampling

cannot be achieved.

AD7441/

AD7451*

ADSP-21xx*

SCLK

DR

RFS

TFS

SCLK

SDATA

CS

*ADDITIONAL PINS REMOVED FOR CLARITY.

Figure 33. Interfacing to the ADSP-21xx