M95320 datasheet(20/44 Pages) STMICROELECTRONICS

20 / 44 page

Instructions

M95320, M95320-W, M95320-R

20/44

Doc ID 5711 Rev 12

The protection features of the device are summarized in Table 5.

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register provided that the Write Enable

Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless

of whether Write Protect (W) is driven high or low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W):

●

If Write Protect (W) is driven high, it is possible to write to the Status Register provided

that the Write enable latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction.

●

If Write Protect (W) is driven low, it is not possible to write to the Status Register even if

the Write Enable latch (WEL) bit has previously been set by a Write Enable (WREN)

instruction. (Attempts to write to the Status Register are rejected, and are not accepted

for execution). As a consequence, all the data bytes in the memory area that are

software-protected (SPM) by the Block protect (BP1, BP0) bits in the Status Register,

are also hardware-protected against data modification.

Regardless of the order of the two events, the Hardware-protected mode (HPM) can be

entered:

●

by setting the Status register write disable (SRWD) bit after driving Write Protect (W)

low

●

or by driving Write Protect (W) low after setting the Status register write disable

(SRWD) bit.

The only way to exit the Hardware-protected mode (HPM) once entered is to pull Write

Protect (W) high.

If Write Protect (W) is permanently tied high, the Hardware-protected mode (HPM) can

never be activated, and only the Software-protected mode (SPM), using the Block protect

(BP1, BP0) bits in the Status Register, can be used.

Table 5.

Protection modes

signal

SRWD

bit

Mode

Write protection of the Status Register

Memory content

Protected area(1) Unprotected area(1)

Software

protected

(SPM)

Status Register is Writable (if the WREN

instruction has set the WEL bit)

The values in the BP1 and BP0 bits can be

changed

Write Protected

Ready to accept

Write instructions

Hardware

protected

(HPM)

Status Register is Hardware write protected

The values in the BP1 and BP0 bits cannot

be changed

Write Protected

Ready to accept

Write instructions

As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.

Table 6.

Address range bits(1)

b15 to b12 are Don’t Care.

Device

32 Kbit devices

Address bits

A11-A0

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