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LTM4627

4627f

APPLICATIONS INFORMATION

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacriﬁcing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably deﬁne and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the μModule and the speciﬁed PCB with all

of the correct material coefﬁcients along with accurate

power loss source deﬁnitions; (2) this model simulates

a software-deﬁned JEDEC environment consistent with

JSED51-9 to predict power loss heat ﬂow and temperature

readings at different interfaces that enable the calculation of

the JEDEC-deﬁned thermal resistance values; (3) the model

and FEA software is used to evaluate the μModule with

heat sink and airﬂow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled-environment

chamber while operating the device at the same power

loss as that which was simulated. An outcome of this

process and due-diligence yields a set of derating curves

provided in other sections of this data sheet. After these

laboratory test have been performed and correlated to the

μModule model, then the

θJBandθBAaresummedtogether

to correlate quite well with the μModule model with no

airﬂow or heat sinking in a properly deﬁne chamber. This

θJB + θBA value is shown in the Pin Conﬁguration section

and should accurately equal the

θJA value because ap-

proximately 100% of power loss ﬂows from the junction

through the board into ambient with no airﬂow or top

mounted heat sink.

The 1.2V and 3.3V power loss curves in Figures 7 and 8

can be used in coordination with the load current derating

curves in Figures 9 to 16 for calculating an approximate

θJA thermal resistance for the LTM4627 with various heat

sinking and airﬂow conditions. The power loss curves

are taken at room temperature, and are increased with

multiplicative factors according to the ambient tempera-

ture. These approximate factors are: 1 for 40°C; 1.05 for

50°C; 1.1 for 60°C; 1.15 for 70°C; 1.2 for 80°C; 1.25 for

90°C; 1.3 for 100°C; 1.35 for 110°C and 1.4 for 120°C.

The derating curves are plotted with the output current

starting at 15A and the ambient temperature at 40°C. The

output voltages are 1.2V, and 3.3V. These are chosen to

include the lower and higher output voltage ranges for

correlating the thermal resistance. Thermal models are

derived from several temperature measurements in a con-

trolled temperature chamber along with thermal modeling

analysis. The junction temperatures are monitored while

ambient temperature is increased with and without airﬂow.

The power loss increase with ambient temperature change

is factored into the derating curves. The junctions are

maintained at 120°C maximum while lowering output

current or power with increasing ambient temperature.

The decreased output current will decrease the inter-

80421 F05

μMODULE DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

CASE (BOTTOM)-TO-BOARD

RESISTANCE

Figure 6. Graphical Representation of JESD 51-12 Thermal Coefﬁcients

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