PSD813F2 datasheet(79/128 Pages) STMICROELECTRONICS

79 / 128 page

PSD8XXFX

Power management

Doc ID 7833 Rev 7

79/128

Power management

All PSD devices offer configurable power saving options. These options may be used

individually or in combinations, as follows:

●

All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are

built with power management technology. In addition to using special silicon design

methodology, power management technology puts the memories into standby mode

when address/data inputs are not changing (zero DC current). As soon as a transition

occurs on an input, the affected memory “wakes up”, changes and latches its outputs,

then goes back to Standby. The designer does not have to do anything special to

achieve memory Standby mode when no inputs are changing—it happens

automatically.

The PLD sections can also achieve Standby mode when its inputs are not changing, as

described in the sections on the Power Management mode registers (PMMR).

●

As with the Power Management mode, the Automatic Power Down (APD) block allows

the PSD to reduce to standby current automatically. The APD Unit can also block MCU

address/data signals from reaching the memories and PLDs. This feature is available

on all the devices of the PSD family. The APD Unit is described in more detail in

Section 17.1: Automatic Power-down (APD) Unit and Power-down mode.

Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity

for a certain time period (MCU is asleep), the APD Unit initiates Power-down mode (if

enabled). Once in Power-down mode, all address/data signals are blocked from

reaching PSD memory and PLDs, and the memories are deselected internally. This

allows the memory and PLDs to remain in Standby mode even if the address/data

signals are changing state externally (noise, other devices on the MCU bus, etc.). Keep

in mind that any unblocked PLD input signals that are changing states keeps the PLD

out of Standby mode, but not the memories.

●

PSD Chip Select input (CSI, PD2) can be used to disable the internal memories,

placing them in Standby mode even if inputs are changing. This feature does not block

any internal signals or disable the PLDs. This is a good alternative to using the APD

Unit. There is a slight penalty in memory access time when PSD Chip Select input

(CSI, PD2) makes its initial transition from deselected to selected.

●

The PMMRs can be written by the MCU at run-time to manage power. All PSD

supports “blocking bits” in these registers that are set to block designated signals from

reaching both PLDs. Current consumption of the PLDs is directly related to the

composite frequency of the changes on their inputs (see Figure 34 and Figure 35).

Significant power savings can be achieved by blocking signals that are not used in

DPLD or CPLD logic equations.

PSD devices have a Turbo Bit in PMMR0. This bit can be set to turn the Turbo mode off

(the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can

achieve standby current when no PLD inputs are changing (zero DC current). Even

when inputs do change, significant power can be saved at lower frequencies (AC

current), compared to when Turbo mode is on. When the Turbo mode is on, there is a

significant DC current component and the AC component is higher.

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