PSD813F2 datasheet(20/128 Pages) STMICROELECTRONICS

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PSD architectural overview

PSD8XXFX

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Doc ID 7833 Rev 7

PSD architectural overview

PSD devices contain several major functional blocks. Figure 4 shows the architecture of the

PSD device family. The functions of each block are described briefly in the following

sections. Many of the blocks perform multiple functions and are user configurable.

3.1

Memory

Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed

discussion can be found in Section 6.1: Memory blocks.

The 1 Mbit or 2 Mbit (128K x 8, or 256K x 8) Flash memory is the primary memory of the

PSD. It is divided into 8 equally-sized sectors that are individually selectable.

The optional 256 Kbit (32K x 8) secondary Flash memory is divided into 4 equally-sized

sectors. Each sector is individually selectable.

The optional SRAM is intended for use as a scratch-pad memory or as an extension to the

MCU SRAM.

Each sector of memory can be located in a different address space as defined by the user.

The access times for all memory types includes the address latching and DPLD decoding

time.

3.2

Page register

The 8-bit Page register expands the address range of the MCU by up to 256 times. The

paged address can be used as part of the address space to access external memory and

peripherals, or internal memory and I/O. The Page register can also be used to change the

address mapping of sectors of the Flash memories into different memory spaces for IAP.

3.3

PLDs

The device contains two PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as

shown in Table 4, each optimized for a different function. The functional partitioning of the

PLDs reduces power consumption, optimizes cost/performance, and eases design entry.

The DPLD is used to decode addresses and to generate Sector Select signals for the PSD

internal memory and registers. The DPLD has combinatorial outputs. The CPLD has 16

Output macrocells (OMC) and 3 combinatorial outputs. The PSD also has 24 input

macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their

inputs from the PLD input bus and are differentiated by their output destinations, number of

product terms, and macrocells.

The PLDs consume minimal power. The speed and power consumption of the PLD is

controlled by the Turbo Bit in PMMR0 and other bits in the PMMR2. These registers are set

by the MCU at run-time. There is a slight penalty to PLD propagation time when invoking the

power management features.

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