数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

PSD813F2 数据表(PDF) 86 Page - STMicroelectronics

部件名 PSD813F2
功能描述  Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V
PDF  128 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

PSD813F2 数据表(HTML) 86 Page - STMicroelectronics

Back Button PSD813F2 Datasheet HTML 82Page - STMicroelectronics PSD813F2 Datasheet HTML 83Page - STMicroelectronics PSD813F2 Datasheet HTML 84Page - STMicroelectronics PSD813F2 Datasheet HTML 85Page - STMicroelectronics PSD813F2 Datasheet HTML 86Page - STMicroelectronics PSD813F2 Datasheet HTML 87Page - STMicroelectronics PSD813F2 Datasheet HTML 88Page - STMicroelectronics PSD813F2 Datasheet HTML 89Page - STMicroelectronics PSD813F2 Datasheet HTML 90Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 86 / 128 page
background image
Reset timing and device status at reset
PSD8XXFX
86/128
Doc ID 7833 Rev 7
Figure 33.
Reset (RESET) timing
tNLNH-PO
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
tOPR
VCC
V
CC(min)
Power-On Reset
Warm Reset
Table 34.
Status during Power-on reset, Warm reset and Power-down mode
Port configuration
Power-on reset
Warm reset
Power-down mode
MCU I/O
Input mode
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out
Tri-stated
Tri-stated
Not defined
Data port
Tri-stated
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Register
Power-on reset
Warm reset
Power-down mode
PMMR0 and PMMR2
Cleared to '0'
Unchanged
Unchanged
Macrocells flip-flop status
Cleared to '0' by internal
Power-On Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM register(1)
Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configuration menu
Unchanged
All other registers
Cleared to '0'
Cleared to '0'
Unchanged
1.
The SR_cod and Periphmode bits in the VM register are always cleared to '0' on Power-on reset or Warm reset.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com