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TLE7239GS 数据表(PDF) 32 Page - Infineon Technologies AG

部件名 TLE7239GS
功能描述  8 Channel High-Side and Low-Side Relay Switch with Limp Home Mode and Cranking
PDF  37 Pages
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制造商  INFINEON [Infineon Technologies AG]
网页  http://www.infineon.com
标志 INFINEON - Infineon Technologies AG

TLE7239GS 数据表(HTML) 32 Page - Infineon Technologies AG

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TLE7239GS
Serial Peripheral Interface (SPI)
Data Sheet
32
Rev. 1.0, 2008-10-30
9.6
Electrical Characteristics
Unless otherwise specified:
V
DD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values:
V
DD = 5.0 V, VBAT = 13.5 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
Unit Test Conditions
min.
typ.
max.
Input Characteristics (CS, SCLK, SI)
9.6.1 L level of pin
CS
SCLK
SI
V
CS(L)
V
SCLK(L)
V
SI(L)
0
0.2*
V
DD V–
9.6.2 H level of pin
CS
SCLK
SI
V
CS(H)
V
SCLK(H)
V
SI(H)
0.5*
V
DD
V
DD
V–
9.6.3 L-input pull-up current through CS
I
CS(L)
540
90
µA
V
CS = 0 V
V
DD = 5 V
9.6.4 H-input pull-up current through CS
I
CS(H)
2.5
µA
1)
V
DD = 5 V
V
CS = 0.5*VDD
9.6.5 L-input pull-down current through pin
SCLK
SI
I
SCLK(L)
I
SI(L)
1.5
µA
1)
V
DD = 5 V
V
SCLK = VSI = 0.2*VDD
9.6.6 H-input pull-down current through pin
SCLK
SI
I
SCLK(H)
I
SI(H)
10
40
80
µA
1)
V
DD= 5 V
V
SCLK = VSI = VDD
Output Characteristics (SO)
9.6.7 L level output voltage
V
SO(L)
0–
0.4
V
I
SO = +2 mA
9.6.8 H level output voltage
V
SO(H)
V
DD -
0.4 V
V
DD
I
SO = -1.5 mA
9.6.9 Output tristate leakage current
I
SO(OFF)
-10
10
µA
V
CS = VDD
Timings
9.6.10 Serial clock frequency
f
SCLK
0–
5
MHz –
9.6.11 Serial clock period
t
SCLK(P)
200
ns
9.6.12 Serial clock high time
t
SCLK(H)
50
ns
1)
9.6.13 Serial clock low time
t
SCLK(L)
50
ns
1)
9.6.14 Enable lead time (falling CS to rising
SCLK)
t
CS(lead)
250
ns
1)
9.6.15 Enable lag time (falling SCLK to rising
CS )
t
CS(lag)
250
ns
1)
9.6.16 Transfer delay time (rising CS to
falling CS )
t
CS(td)
250
ns
1)
9.6.17 Data setup time (required time SI to
falling SCLK)
t
SI(su)
20
ns
1)
9.6.18 Data hold time (falling SCLK to SI)
t
SI(h)
20
ns
1)



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