TLE7239GS

Electrical Characteristics

Data Sheet

12

Rev. 1.0, 2008-10-30

4.3

Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards.

For more information, go to www.jedec.org.

1) Not subject to production test

Pos.

Parameter

Symbol

Limit Values

Unit

Conditions

Min.

Typ.

Max.

4.3.1

Junction to Case, bottom

R

thJC,back

––

25

K/W

2)

2) Specified

R

T

4.3.2

Junction to Case, top

R

thJC,top

––

25

K/W

2)

4.3.3

Junction to Pin (1,2,11 or 12)

R

thJPin

––

17

K/W

2)

4.3.4

Junction to Ambient

(1s0p, min. footprint)

R

thJA,min

–90

–

K/W

3)

3) Specified

R

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with minimal footprint copper area and 70

µm thickness.

T

4.3.5

Junction to Ambient

R

thJA,300

–

70

–

K/W

4)

4) Specified

R

and 70

4.3.6

Junction to Ambient

R

thJA,600

–

65

–

K/W

5)

5) Specified

R

and 70

4.3.7

Junction to Ambient (2s2p)

R

thJA,2s2p

–

55

–

K/W

6)

6) Specified

R

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70

µm Cu, 2 x 35 µm Cu).

T