MPC8535E datasheet(49/126 Pages) FREESCALE

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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

Figure 23 shows the TBI receive AC timing diagram.

Figure 23. TBI Receive AC Timing Diagram

2.9.2.5

TBI Single-Clock Mode AC Specifications

When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant eTSEC interface.

In single-clock TBI mode, when a 125-MHz TBI receive clock is supplied on TSECn pin (no receive clock is used on in this

mode, whereas for the dual-clock mode this is the PMA0 receive clock). The 125-MHz transmit clock is applied on the in all

TBI modes.

A summary of the single-clock TBI mode AC specifications for receive appears in Table 34.

Table 34. TBI single-clock Mode Receive AC Timing Specification

At recommended operating conditions with LVDD/TVDD of 3.3 V ± 5%

Parameter/Condition

Symbol

Min

Typ

Max

Unit

RX_CLK clock period

tTRR

7.5

8.0

8.5

RX_CLK duty cycle

tTRRH

RX_CLK peak-to-peak jitter

tTRRJ

——

250

Rise time RX_CLK (20%–80%)

tTRRR

——

1.0

Fall time RX_CLK (80%–20%)

tTRRF

——

1.0

RCG[9:0] setup time to RX_CLK rising edge

tTRRDV

2.0

——ns

RCG[9:0] hold time to RX_CLK rising edge

tTRRDX

1.0

——ns

TBI Receive Clock 1

RCG[9:0]

tTRX

tTRXH

tTRXR

tTRXF

tTRDVKH

TBI Receive Clock 0

tTRDXKH

tTRDVKH

tTRDXKH

tSKTRX

tTRXH

Valid Data

(TSECn_TX_CLK)

(TSECn_RX_CLK)

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