MPC8535E datasheet(75/126 Pages) FREESCALE

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Enhanced Secure Digital Host Controller (eSDHC)

MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

2.13.2

eSDHC AC Timing Specifications

Table 56 provides the eSDHC AC timing specifications as defined in Figure 44.

Output low voltage

VOL

IOL = 100uA @OVDDmin

—

0.125 * OVDD

—

Output high voltage

VOH

IOH = -100 uA

OVDD - 0.2

—

Output low voltage

VOL

IOL = 2 mA

—

0.3

—

Notes:

1. The min VIL and VIH values are based on the respective min and max OVIN values found in Table 3.

2. Open drain mode for MMC cards only.

Table 56. eSDHC AC Timing Specifications

At recommended operating conditions (see Table 3)

Parameter

Symbol1

Min

Max

Unit

Notes

SD_CLK clock frequency:

SD/SDIO Full speed/high speed mode

MMC Full speed/high speed mode

fSHSCK

25/50

20/52

MHz

2, 5

SD_CLK clock frequency - identification mode

fSIDCK

100

400

KHz

3, 5

SD_CLK clock low time - High speed/Full speed mode

tSHSCKL

7/10

—

SD_CLK clock high time - High speed/Full speed mode

tSHSCKH

7/10

—

SD_CLK clock rise and fall times

tSHSCKR/

tSHSCKF

—3

Input setup times: SD_CMD, SD_DATx, SD_CD to

SD_CLK

tSHSIVKH

5—

Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK

tSHSIXKH

2.5

—

4,5

Output delay time: SD_CLK to SD_CMD, SD_DATx valid

tSHSKHOV

–3

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC

high speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching

the invalid state (X) or output hold time. Note that, in general, the clock reference symbol representation is based on five letters

representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

2. In full speed mode, clock frequency value can be 0–25 MHz for a SD/SDIO card and 0–20 MHz for a MMC card. In high speed

mode, clock frequency value can be 0–50 MHz for a SD/SDIO card and 0–52MHz for a MMC card.

3. 0 Hz means to stop the clock. The given minimum frequency range is for cases were a continuous clock is required.

4. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2ns.

5. CCARD ≤10 pF, (1 card), and CL = CBUS + CHOST+CCARD ≤ 40 pF

Table 55. eSDHC interface DC Electrical Characteristics (continued)

At recommended operating conditions (see Table 3)

Characteristic

Symbol

Condition

Min

Max

Unit

Notes

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