AD7468BRT-R datasheet(22/28 Pages) AD

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AD7466/AD7467/AD7468

Rev. C | Page 22 of 28

SERIAL INTERFACE

Figure 29, Figure 30, and Figure 31 show the timing diagrams

for serial interfacing to the AD7466/AD7467/AD7468. The

serial clock provides the conversion clock and controls the

transfer of information from the ADC during a conversion.

The part begins to power up on the CS falling edge. The falling

edge of CS puts the track-and-hold into track mode and takes

the bus out of three-state. The conversion is also initiated at this

point. On the third SCLK falling edge after the CS falling edge,

the part should be powered up fully at Point B, as shown in

Figure 29, and the track-and-hold returns to hold.

For the AD7466, the SDATA line goes back into three-state and

the part enters power-down on the 16th SCLK falling edge. If

the rising edge of CS occurs before 16 SCLKs elapse, the

conversion terminates, the SDATA line goes back into three-

state, and the part enters power-down; otherwise SDATA

returns to three-state on the 16th SCLK falling edge, as shown

in Figure 29. Sixteen serial clock cycles are required to perform

the conversion process and to access data from the AD7466.

For the AD7467, the 14th SCLK falling edge causes the SDATA

line to go back into three-state, and the part enters power-down.

If the rising edge of CS occurs before 14 SCLKs elapse, the con-

version terminates, the SDATA line goes back into three-state,

and the AD7467 enters power-down; otherwise SDATA returns

to three-state on the 14th SCLK falling edge, as shown in Figure 30.

Fourteen serial clock cycles are required to perform the

conversion process and to access data from the AD7467.

For the AD7468, the 12th SCLK falling edge causes the SDATA

line to go back into three-state, and the part enters power-

down. If the rising edge of CS occurs before 12 SCLKs elapse,

the conversion terminates, the SDATA line goes back into three-

state, and the AD7468 enters power-down; otherwise SDATA

returns to three-state on the 12th SCLK falling edge, as shown

in Figure 31. Twelve serial clock cycles are required to perform

the conversion process and to access data from the AD7468.

CS going low provides the first leading zero to be read in by the

microcontroller or DSP. The remaining data is then clocked out

by subsequent SCLK falling edges, beginning with the second

leading zero; thus, the first clock falling edge on the serial clock

has the first leading zero provided and also clocks out the

second leading zero. For the AD7466, the final bit in the data

transfer is valid on the 16th SCLK falling edge, having been

clocked out on the previous (15th) SCLK falling edge.

In applications with a slow SCLK, it is possible to read in data

on each SCLK rising edge. In such a case, the first falling edge

of SCLK after the CS falling edge clocks out the second leading

zero and can be read in the following rising edge. If the first

SCLK edge after the CS falling edge is a falling edge, the first

leading zero that was clocked out when CS went low is missed,

unless it is not read on the first SCLK falling edge. The 15th

falling edge of SCLK clocks out the last bit, and it can be read in

the following rising SCLK edge.

If the first SCLK edge after the CS falling edge is a rising edge, CS

clocks out the first leading zero, and it can be read on the SCLK

rising edge. The next SCLK falling edge clocks out the second

leading zero, and it can be read on the following rising edge.

SCLK

tCONVERT

tQUIET

DB11

DB10

DB2

DB1

DB0

4 LEADING ZEROS

THREE-STATE

SDATA

12 BITS OF DATA

Figure 29. AD7466 Serial Interface Timing Diagram

tQUIET

SCLK

SDATA

4 LEADING ZEROS

THREE-STATE

10 BITS OF DATA

DB9

DB8

DB0

tCONVERT

Figure 30. AD7467 Serial Interface Timing Diagram

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