LTC4263 datasheet(21/28 Pages) LINER

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LTC4274

4274fa

APPLICATIONS INFORMATION

even at extended 802.3at power levels. Current limit and

foldback behavior are programmable. Figure 14 shows

MOSFET power dissipation with 802.3af-style foldback

compared with a typical MOSFET SOA curve; Figure 15

demonstrates how two-stage foldback keeps the FET

within its SOA under the same conditions. Table 4 gives

examples of recommended ILIM register settings.

The LTC4274 will support current levels well beyond the

maximum values in the 802.3at specification. The shaded

areas in Table 5 indicate settings that may require a larger

external MOSFET, additional heat sinking, or a reduced

tLIM setting.

MOSFET Fault Detection

LTC4274 PSE ports are designed to tolerate significant

levels of abuse, but in extreme cases it is possible for the

external MOSFET to be damaged. A failed MOSFET may

short source to drain, which will make the port appear to

be on when it should be off; this condition may also cause

the sense resistor to fuse open, turning off the port but

causing the LTC4274 SENSE pin to rise to an abnormally

high voltage. A failed MOSFET may also short from gate

to drain, causing the LTC4274 GATE pin to rise to an ab-

normally high voltage. The LTC4274 SENSE and GATE pins

are designed to tolerate up to 80V faults without damage.

If the LTC4274 sees any of these conditions for more than

180μs, it disables all port functionality, reduces the gate

drive pull-down current for the port and reports a FET Bad

fault. This is typically a permanent fault, but the host can

attempt to recover by resetting the port, or by resetting

the entire chip if a port reset fails to clear the fault. If the

MOSFET is in fact bad, the fault will quickly return, and

the port will disable itself again.

An open or missing MOSFET will not trigger a FET Bad

fault, but will cause a tSTART fault if the LTC4274 attempts

to turn on the port.

Voltage and Current Readback

The LTC4274 measures the output voltage and current

at each port with an internal A/D converter. Port data is

only valid when the port power is on. The converter has

two modes:

• Slow mode: 14 samples per second, 14.5 bits resolution

• Fast mode: 440 samples per second, 9.5 bits resolution

In fast mode, the least significant 5 bits of the lower byte are

zeroes so that bit scaling is the same in both modes.

Disconnect

The LTC4274 monitors the port to make sure that the PD

continues to draw the minimum specified current. A dis-

connect timer counts up whenever port current is below

7.5mA (typ), indicating that the PD has been disconnected.

If the tDIS timer expires, the port will be turned off and

the disconnect bit in the fault event register will be set.

If the current returns before the tDIS timer runs out, the

Figure 14. Turn On Currents vs FET Safe Operating

Area at 90°C Ambient

Figure 15. LTC4274 Foldback vs FET Safe Operating

Area at 90°C Ambient

PD Voltage (V) at VPSE = 58V

0.0

0.2

0.4

0.6

4274 F14

0.8

1.0

0.1

0.3

0.5

0.7

0.9

802.3af FOLDBACK

SOA DC AT 90°C

PD Voltage (V) at VPSE = 58V

0.0

0.2

0.4

0.6

4274 F15

0.8

1.0

0.1

0.3

0.5

0.7

0.9

802.3af FOLDBACK

SOA DC AT 90°C

SOA

75ms

90°C

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