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LTC4274

4274fa

timer resets and will start counting from the beginning

if the undercurrent condition returns. As long as the PD

exceeds the minimum current level more often than tDIS,

it will stay powered.

Although not recommended, the DC disconnect feature

can be disabled by clearing the DC Disconnect Enable

bit. Note that this defeats the protection mechanisms

built into the IEEE spec, since a powered port will stay

powered after the PD is removed. If the still-powered port

is subsequently connected to a non-PoE data device, the

device may be damaged.

The LTC4274 does not include AC disconnect circuitry, but

includes an AC disconnect enable bit to maintain compat-

ibility with the LTC4259A. If the AC Disconnect Enable bit

is set, DC disconnect will be used.

Shutdown Pin

The LTC4274 includes a hardware SHDN pin. When the

SHDN pin is pulled to DGND, the port will be shut off im-

mediately. The port remains shut down until re-enabled

via I2C or a device reset in AUTO pin mode.

Masked Shutdown

The LTC4274 provides a low latency port shedding fea-

ture to quickly reduce the system load when required. By

allowing a pre-determined set of ports to be turned off,

the current on an overloaded main power supply can be

reduced rapidly while keeping high priority devices pow-

ered. Each port can be configured to high or low priority;

all low-priority ports will shut down within 6.5μs after the

MSD pin is pulled low. If a port is turned off via MSD, the

corresponding Detection and Classification Enable bits are

cleared, so the port will remain off until the host explicitly

re-enables detection.

SERIAL DIGITAL INTERFACE

Overview

The LTC4274 communicates with the host using a standard

SMBus/I2C 2-wire interface. The LTC4274 is a slave-only

device, and communicates with the host master using

the standard SMBus protocols. Interrupts are signaled to

the host via the INT pin. The Timing Diagrams (Figures 5

through 9) show typical communication waveforms and

their timing relationships. More information about the

SMBus data protocols can be found at www.smbus.org.

The LTC4274 requires both the VDD and VEE supply rails

to be present for the serial interface to function.

Bus Addressing

The LTC4274’s primary serial bus address is 010xxxxb,

with the lower four bits set by the AD3-AD0 pins; this

allows up to 16 LTC4274s on a single bus. All LTC4274s

also respond to the address 0110000b, allowing the host

to write the same command (typically configuration com-

mands) to multiple LTC4274s in a single transaction. If the

LTC4274 is asserting the INT pin, it will also respond to the

alert response address (0001100b) per the SMBus spec.

Interrupts and SMBAlert

Most LTC4274 port events can be configured to trigger

an interrupt, asserting the INT pin and alerting the host

to the event. This removes the need for the host to poll

the LTC4274, minimizing serial bus traffic and conserving

host CPU cycles. Multiple LTC4274s can share a common

INT line, with the host using the SMBAlert protocol (ARA)

to determine which LTC4274 caused an interrupt.

For information on serial bus usage and device configura-

tion and status, refer to the LTC4274 Software Program-

ming documentation.

EXTERNAL COMPONENT SELECTION

Power Supplies and Bypassing

The LTC4274 requires two supply voltages to operate. VDD

requires 3.3V (nominally) relative to DGND. VEE requires

a negative voltage of between –44V and –57V for Type 1

PSEs, or –50V to –57V for Type 2 PSEs, relative to AGND.

The relationship between the two grounds is not fixed;

AGND can be referenced to any level from VDD to DGND,

although it should typically be tied to either VDD or DGND.

APPLICATIONS INFORMATION

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