LTC4263 datasheet(23/28 Pages) LINER

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LTC4274

4274fa

APPLICATIONS INFORMATION

VDD provides power for most of the internal LTC4274 cir-

cuitry, and draws a maximum of 3mA. A ceramic decoupling

cap of at least 0.1μF should be placed from VDD to DGND,

as close as practical to each LTC4274 chip.

Figure 16 shows a three component low dropout regulator

for a negative supply to DGND generated from the negative

VEE supply. VDD is tied to AGND and DGND is negative

referenced to AGND. This regulator drives a single LTC4274

device. In Figure 17, DGND is tied to AGND in this boost

converter circuit for a positive VDD supply of 3.3V above

AGND. This circuit can drive multiple LTC4274 devices

and opto couplers.

VEE is the main supply that provides power to the PD.

Because it supplies a relatively large amount of power and

is subject to significant current transients, it requires more

design care than a simple logic supply. For minimum IR

loss and best system efficiency, set VEE near maximum

amplitude (57V), leaving enough margin to account for

transient over- or undershoot, temperature drift, and the

line regulation specs of the particular power supply used.

Bypass capacitance between AGND and VEE is very impor-

tant for reliable operation. If a short circuit occurs at the

output port it can take as long as 1μs for the LTC4274 to

begin regulating the current. During this time the current

is limited only by the small impedances in the circuit and

a high current spike typically occurs, causing a voltage

transient on the VEE supply and possibly causing the

LTC4274 to reset due to a UVLO fault. A 1μF, 100V X7R

capacitor placed near the VEE pin is recommended to

minimize spurious resets.

Isolating the Serial Bus

The LTC4274 includes a split SDA pin (SDAIN and SDAOUT)

to ease opto-isolation of the bidirectional SDA line.

IEEE 802.3 Ethernet specifications require that network

segments (including PoE circuitry) be electrically isolated

from the chassis ground of each network interface device.

However, network segments are not required to be isolated

Figure 17. Positive VDD Boost Converter

Figure 16. Negative LDO to DGND

4274 F17

R54

56k

C79

2200pF

GND

ITH/RUN

LTC3803

VCC

VFB

NGATE

Q15

FDC2512

Q13

FMMT723

Q14

FMMT723

SENSE

VEE

C74

100μF

6.3V

C75

10μF

16V

100μH

SUMIDA CDRH5D28-101NC

R51

4.7k

R53

4.7k

R52

3.32k

3.3V AT 400mA

R55

806Ω

R59

0.100Ω

1%, 1W

R56

47.5k

R57

D28

B1100

R58

10Ω

R60

10Ω

C73

10μF

6.3V

10μH

SUMIDA CDRH4D28-100NC

C77

0.22μF

100V

C78

0.22μF

100V

C76

10μF

63V

PD VOLTAGE (V)

0.0

0.2

0.6

1.0

4274 F16

1.4

0.4

0.8

1.2

802.3af FOLDBACK

SOA

75ms

90°C

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