AD7280ABSTZ datasheet(32/48 Pages) AD

32 / 48 page

AD7280A

Rev. 0 | Page 32 of 48

SERIAL INTERFACE

The AD7280A serial interface is Mode 1 SPI compliant, that is,

the clock polarity (CPOL) is 0, and the clock phase (CPHA) is 1.

The interface consists of four signals: CS, SCLK, SDI, and SDO.

The SDI line is used to transfer data into the on-chip registers,

and the SDO line is used to read the on-chip registers and

conversion result registers. SCLK is the serial clock input for the

device; all data transfers, either on SDI or on SDO, take place

with respect to SCLK. Data is clocked into the AD7280A on the

SCLK falling edge. Data is clocked out of the AD7280A on the

SCLK rising edge. The CS input is used to frame the serial data

being transferred to or from the device.

The AD7280A allows 32-bit data transfer only and resets a

counter on the rising edge of CS to ensure that the AD7280A is

automatically resynchronized with the DSP/microprocessor on

every falling edge of CS. Individual 8-bit or 16-bit words can be

used to assemble a 32-bit command, but a single 32-bit wide CS

frame is required to correctly structure the assembly of the

32-bit command.

The rising edge of CS can also be used to initiate the sequence of

conversions by writing to the upper byte of the control register.

shows the timing diagram for the serial interface of the

AD7280A. See the

section for more

information about the daisy-chain interface.

Figure 2

Daisy-Chain Interface

WRITING TO THE AD7280A

In a battery monitoring application, up to eight AD7280As can

be daisy-chained to allow up to 48 individual Li-Ion cell voltages

to be monitored. Each write operation must, therefore, include

a device address and a register address, in addition to the data

to be written. An additional identifier bit is also required when

addressing all AD7280As in the daisy chain. The AD7280A SPI

interface, in combination with the daisy-chain interface, allows

any register in the stack of eight AD7280As to be updated using

one 32-bit write cycle. The 32-bit write sequence is shown in

Table 20. The AD7280A also requires an 8-bit CRC to be

included in each write command.

Device Address

The device address is a 5-bit address that allows each individual

AD7280A in the battery monitoring stack to be uniquely

identified. On initial power-up, each AD7280A is configured

with a default address of 0x00. A simple sequence of commands

allows each AD7280A to recognize its unique device address in

the stack (see the Initializing the AD7280A section).

This device address can then be locked to the AD7280A and used

in subsequent read and write commands. The device address is

written to and read from the AD7280A stack in reverse order,

that is, LSB first.

The register map for the AD7280A is provided in Table 13. Each

reading from the on-chip registers of the AD7280A.

When issuing a write command to a part in the stack of

AD7280A devices, the data to be written is an 8-bit word. As

shown in Table 13, all read/write registers are eight bits wide.

For more information about the correct settings for each

Address All Parts

The AD7280A allows write commands to be issued simultane-

ously to all devices in the daisy chain, as well as write commands to

individual AD7280As. A write to all devices in the daisy chain is

completed by setting Bit D12 of the write command to 1. When

issuing a write all command, the device address should be set to

0x00. This device address is also used to calculate the 8-bit CRC

for transmission with the write all command.

8-Bit CRC

The AD7280A includes an 8-bit cyclic redundancy check (CRC)

on all write commands to either individual devices or to a chain

of devices. An AD7280A that receives an invalid CRC in the

write command does not execute the command. The CRC on

the write command is calculated based on Bits[D31:D11] of the

write command. These bits include the device address, the

and Bit D11. For more information about the CRC, see the

Cyclic Redundancy Check section.

Bit Pattern (010)

A required fixed bit pattern of 010 to Bits[D2:D0] of the 32-bit

write command of the AD7280A provides an additional stage of

verification. The correct position of this bit pattern is verified

on each write command received by the AD7280A. An

AD7280A that receives an incorrect bit pattern in the write

command does not execute the command.

Table 20. 32-Bit Write Cycle

Device Address1

Address All Parts

Reserved (0 Bit)

8-Bit CRC

Bit Pattern (010)

D31 to D27

D26 to D21

D20 to D13

D12

D11

D10 to D3

D2 to D0

1 The device address is configured LSB first. For example, to address the second device in the stack, that is, the first slave device, the sequence of bits input to the

AD7280A should be 10000. The register address, data bits, and CRC bits are input MSB first.

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