AD7280ABSTZ datasheet(19/48 Pages) AD

19 / 48 page

AD7280A

Rev. 0 | Page 19 of 48

REFERENCE

The internal reference is temperature compensated to 2.5 V. The

reference is trimmed to provide a typical drift of ±3 ppm/°C. As

shown in Figure 30, the internal reference circuitry consists of a

1.2 V band gap reference and a reference buffer. The 2.5 V refer-

ence is available at the VREF pin. The VREF pin should be decoupled

to REFGND using a 1 μF or greater ceramic capacitor. The CREF

pin should be decoupled to REFGND using a 0.1 μF or greater

ceramic capacitor. The 2.5 V reference is capable of driving an

external load of up to 10 kΩ.

VREF

REFGND

CREF

AVCC

ADC SELF-TEST

VOLTAGE

BAND GAP

1.2V

Figure 30. AD7280A Internal Reference

CONVERTING CELL VOLTAGES AND AUXILIARY

ADC INPUTS

A conversion can be initiated on the AD7280A using either the

CNVST input or the serial interface (see the

section). A single conversion command initiates conver-

sions on all selected channels of the AD7280A. As described in

the

section, the voltage of each individual

battery cell is measured by converting the difference between

adjacent analog inputs. The first cell to be converted following a

convert start command is Cell 6, which is the difference between

VIN6 and VIN5. At the end of the first conversion, the AD7280A

generates an internal end-of-conversion (EOC) signal. This internal

EOC selects the next cell voltage inputs for measurement through

the multiplexer, that is, the difference between VIN5 and VIN4.

The new input is acquired, and a second internal convert start

signal is generated, which initiates the conversion. This process

is repeated until all the selected voltage and auxiliary ADC inputs

have been converted.

Conversion Start

Format

Converter Operation

The conversion sequence—that is, the order in which the cell

voltages and auxiliary ADC inputs are converted—is shown in

Figure 31 and Figure 32. The cell voltage inputs are converted in

reverse order, that is, Cell 6 is followed by Cell 5, and so on.

However, the auxiliary ADC inputs are converted in increasing

numerical order, that is, AUX1 is followed by AUX2, and so on.

For example, when all 12 inputs are selected for conversion, the

conversion of Cell 1, that is, VIN1 to VIN0, is followed by the

conversion of the AUX1 input.

When all selected conversions are completed, the VIN6 and VIN5

voltage inputs are again selected through the multiplexer, and

the voltage across Cell 6 is acquired in preparation for the next

conversion request. This is the default state for the multiplexer.

Bits[D15:D14] of the control register select the cell voltage and

auxiliary ADC inputs to be converted. There are four options

available (see Table 8).

Table 8. Cell Voltage and Auxiliary ADC Input Selection

Bits[D15:D14]

Voltage Inputs

Auxiliary ADC Inputs

6 to 1

1 to 6

6 to 1

1, 3, and 5

6 to 1

None

ADC self-test

None

Each voltage and auxiliary ADC input conversion requires a

minimum of 1 μs to acquire and convert the cell voltage or

auxiliary ADC input voltage. For example, when Bits[D15:D14]

are set to 00, the falling edge of CNVST triggers a series of 12

conversions. This requires a minimum of 12 μs to convert all

selected measurements on a single AD7280A. If no auxiliary

ADC input conversions are required, Bits[D15:D14] are set to

10. In this case, the conversion request triggers a series of six

conversions, requiring a minimum of 6 μs.

tCONV

tACQ

VOLT 6

VOLT 5

VOLT 4

AUX6

INTERNAL ADC

CONVERSIONS

CNVST

Figure 31. ADC Conversions on the AD7280A

tQUIET

tWAIT

INTERNAL ADC

CONVERSIONS

SERIAL READ

OPERATION

CNVST

VOLT

AUX6

VOLT

DATA READBACK — ALL DEVICES

CONVERSION WINDOW

Figure 32. ADC Conversions and Readback on the AD7280A

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