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AD7280ABSTZ 数据表(PDF) 24 Page - Analog Devices |
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AD7280ABSTZ 数据表(HTML) 24 Page - Analog Devices |
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24 / 48 page  AD7280A Rev. 0 | Page 24 of 48 POWER-DOWN The AD7280A provides two power-down options. • Full power-down (hardware) • Software power-down Full Power-Down (Hardware) The AD7280A can be placed into full power-down mode, which requires only 5 μA maximum current, by taking the PD pin low. The falling edge of the PD pin powers down all analog and digital circuitry. The AD7280A includes a digital delay filter on the PD pin, which protects against a power-down being initiated by noise or glitches on the hardware PD pin. A hardware power-down is not initiated until the PD pin is held low for approximately 130 μs. Similarly, the AD7280A is not taken out of power-down mode until the PD pin is held high for approximately 130 μs. The digital delay filter does not apply on initial power-up. The power-on request is accepted by the AD7280A approximately 5 μs after the rising edge of PD. When placing the AD7280A into full power-down mode, AVCC and DVCC must fall to 0 V and must not be held high by any external means. AVCC and DVCC can be held high unintention- ally if the auxiliary ADC inputs are greater than the forward bias on the internal ESD protection diodes. For this reason, it is recommended that the auxiliary ADC inputs return to 0 V when the part is placed in full power-down mode. In addition, all digital inputs on the AD7280A master device must return to 0 V when the part is placed in full power-down mode (see Figure 37). However, if an external VDRIVE supply is used—that is, VDRIVE is not connected to VREG—then only the CNVST line must return low (see ). Figure 38 When the AD7280A is placed into full power-down mode, the device must be left in full power-down for a minimum of 2 ms when the VREG and VREF pins are decoupled with 1 μF capacitors. This ensures that the charge on the VREG and VREF decoupling capacitors dissipates sufficiently to allow the internal power-on reset circuit to activate when powering the AD7280A back up. This time is measured from the falling edge of the PD pin. shows a plot of the voltage on the VREG and VREF pins as the AD7280A is powering down with 1 μF decoupling capacitors on the pins. shows a similar plot but with 10 μF decoupling capacitors on the VREG and VREF pins. Figure 18 Figure 20 VSS AD7280A VREG 0.1µF 10µF 1µF 0.1µF 0.1µF VDD VDD DVCC AVCC 1µF 0.1µF VREF CREF ALERT SDO SCLK SDI VDRIVE MASTER AUX6 AUXTERM AUX5 AUX4 AUX3 AUX2 AUX1 10kΩ MUST GO TO 0V IN HARDWARE POWER-DOWN MUST GO TO 0V IN HARDWARE POWER-DOWN CS PD CNVST DSP/MICRO- PROCESSOR Figure 37. VDRIVE Powered from VREG VSS AD7280A VREG 0.1µF 10µF 1µF 0.1µF 0.1µF VDD VDD 10µF 0.1µF DVCC AVCC 1µF 0.1µF VREF CREF ALERT SDO SCLK SDI VDRIVE MASTER AUX6 AUXTERM AUX5 AUX4 AUX3 AUX2 AUX1 10kΩ MUST GO TO 0V IN HARDWARE POWER-DOWN MUST GO TO 0V IN HARDWARE POWER-DOWN CS PD CNVST DSP/MICRO- PROCESSOR 2.7V TO 5.5V SUPPLY Figure 38. VDRIVE Powered from DSP/Microprocessor |
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