AD7280ABSTZ datasheet(21/48 Pages) AD

21 / 48 page

AD7280A

Rev. 0 | Page 21 of 48

The 10 kΩ resistors in series with the inputs provide protection for

the analog inputs in the event of an overvoltage or undervoltage

on those inputs. The 100 nF capacitor across the differential inputs

acts as a low-pass filter in conjunction with the 10 kΩ resistor.

The cutoff frequency of the low-pass filter is 80 Hz. Using these

external components, the default acquisition time of 400 ns can

be used, which allows a combined acquisition and conversion

time of 1 μs.

CONVERTING CELL VOLTAGES AND AUXILIARY

ADC INPUTS IN A CHAIN OF AD7280As

The AD7280A provides a daisy-chain interface that allows up to

eight parts to be stacked without the need for individual isola-

tion. One feature of the daisy-chain interface is the ability to

initiate conversions on all parts in the daisy-chain stack with a

single convert start command. The convert start command is

transferred up the daisy chain, from the master device to each

AD7280A in turn. The delay time between each AD7280A is

tDELAY, as shown in Figure 34. The maximum delay between the

start of conversions on the master AD7280A and the last AD7280A

device in the chain can be determined by multiplying tDELAY by

the number of slave AD7280As in the daisy chain. The total

conversion time for all cell voltage and auxiliary ADC input

conversions can be calculated using the following equation:

Total Conversion Time = ((tACQ + tCONV) × (Number of

Conversions per Part)) − tACQ + ((N − 1) × tDELAY)

where:

tACQ is the analog input acquisition time of the AD7280A (see

Table 9).

tCONV is the conversion time of the AD7280A, as specified in Table 3.

Number of Conversions per Part is the number of inputs selected

for conversion (6, 9, or 12, as listed in Table 8), multiplied by

the number of averages selected for each input (1, 2, 4, or 8).

N is the number of AD7280As in the daisy chain.

tDELAY is the delay time when transferring the convert start

command between adjacent AD7280A devices, as specified

in Table 3.

The total conversion times calculated for three possible

configurations of the AD7280A are included in Table 10.

tCONV

tACQ + tCONV

VOLT 6

VOLT 5

TOTAL CONVERSION TIME =

((

tACQ + tCONV) × (#CONVERSIONS PER PART)) – tACQ + ((N – 1) × tDELAY)

VOLT 4

AUX6

tDELAY

tACQ + tCONV

tDELAY

VOLT 12

VOLT 11

VOLT 10

AUX12

tACQ + tCONV

VOLT 18

VOLT 17

VOLT 16

AUX18

INTERNAL ADC

CONVERSIONS

PART 1

SERIAL READ

OPERATION

PART 2

SERIAL READ

OPERATION

PART 3

CNVST

Figure 34. ADC Conversions and Readback on a Chain of Three AD7280As

Table 10. Calculated Conversion Times for Three Example AD7280A Configurations, TA = −40°C to +85°C

Bits

[D15:D14]

Bits

[D10:D9]

Bits

[D6:D5]

Configuration

Conversion

Time per Part

Total Conversion Time

per 48 Channel Stack

12 channels; tCONV = 695 ns; tACQ = 465 ns; average = 0

13.46 μs

15.2 μs

12 channels; tCONV = 695 ns; tACQ = 1.01 μs; average = 0

19.45 μs

21.2 μs

12 channels; tCONV = 695 ns; tACQ = 1.46 μs; average = 0

24.4 μs

26.15 μs

12 channels; tCONV = 695 ns; tACQ = 1.89 μs; average = 0

29.13 μs

30.9 μs

6 channels; tCONV = 695 ns; tACQ = 465 ns; average = 0

6.5 μs

8.23 μs

6 channels; tCONV = 695 ns; tACQ = 1.01 μs; average = 0

9.22 μs

10.97 μs

6 channels; tCONV = 695 ns; tACQ = 1.46 μs; average = 0

11.47 μs

13.22 μs

6 channels; tCONV = 695 ns; tACQ = 1.89 μs; average = 0

13.62 μs

15.37 μs

12 channels; tCONV = 695 ns; tACQ = 465 ns; average = 8

110.9 μs

112.65 μs

12 channels; tCONV = 695 ns; tACQ = 1.01 μs; average = 8

162.67 μs

164.42 μs

12 channels; tCONV = 695 ns; tACQ = 1.46 μs; average = 8

205.42 μs

207.17 μs

12 channels; tCONV = 695 ns; tACQ = 1.89 μs; average = 8

246.27 μs

248.02 μs

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