ADP5033ACBZ-1-R7 datasheet(18/28 Pages) AD

18 / 28 page

ADP5033

Rev. 0 | Page 18 of 28

Undervoltage Lockout

To protect against battery discharge, undervoltage lockout (UVLO)

circuitry is integrated in the system. If the input voltage on VIN1

drops below a typical 2.15 V UVLO threshold, all channels shut

down. In the buck channels, both the power switch and the

synchronous rectifier turn off. When the voltage on VIN1 rises

above the UVLO threshold, the part is enabled once more.

Alternatively, the user can select device models with a UVLO

set at a higher level, suitable for USB applications. For these

models, the device reaches the turn-off threshold when the

input supply drops to 3.65 V typical.

In case of a thermal or UVLO event, the active pull-downs (if

factory enabled) are enabled to discharge the output capacitors

quickly. The pull-downs remain engaged until the input supply

voltage or thermal fault event is no longer present.

Enable/Shutdown

The ADP5033 has two enable pins (ENA and ENB). A high

level applied to the enable pins enables a certain selection of

regulators defined by factory programming. For example, the

ADP5033 can be factory programmed to enable BUCK1 and

LDO2 with ENA and BUCK2 and LDO1 with ENB. When both

enables are low, all regulators are turned off. When both enable

pins are high, all regulators are turned on. All possible regulator

combinations can be factory programmed to operate with the

ENA and ENB pins.

Figure 44 shows the regulator activation timings for the

ADP5033 when both enables are connected to VINx. Figure 44

also shows the active pull-down activation.

BUCK1 AND BUCK2

The two bucks use a fixed frequency and high speed current

mode architecture. The bucks operate with an input voltage of

2.3 V to 5.5 V.

Control Scheme

The bucks operate with a fixed frequency, current mode PWM

control architecture at medium to high loads for high efficiency

but shift to a PSM control scheme at light loads to lower the

regulation power losses. When operating in fixed frequency

PWM mode, the duty cycle of the integrated switches is adjusted

and regulates the output voltage. When operating in PSM at

light loads, the output voltage is controlled in a hysteretic

manner, with higher output voltage ripple. During part of this

time, the converter is able to stop switching and enters an idle

mode, which improves conversion efficiency.

PWM Mode

In PWM mode, the bucks operate at a fixed frequency of 3 MHz

set by an internal oscillator. At the start of each oscillator cycle,

the pFET switch is turned on, sending a positive voltage across

the inductor. Current in the inductor increases until the current

sense signal crosses the peak inductor current threshold that

turns off the pFET switch and turns on the nFET synchronous

rectifier. This sends a negative voltage across the inductor,

causing the inductor current to decrease. The synchronous

rectifier stays on for the rest of the cycle. The buck regulates the

output voltage by adjusting the peak inductor current threshold.

VIN1

VOUT3

VOUT4

VOUT1

VUVLO

VOUT2

VPOR

BUCK2

PULL-DOWN

BUCK1, LDO1, LDO2

PULL-DOWNS

50µs (MIN)

30µs (MIN)

50µs (MIN)

30µs (MIN)

Figure 44. Regulators Sequencing on the ADP5033 (ENx = VINx)

ADP5033ACBZ-1-R7 数据表(PDF) 18 Page - Analog Devices

ADP5033ACBZ-1-R7 数据表(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载