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CY8C53 数据表(PDF) 97 Page - Cypress Semiconductor |
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CY8C53 数据表(HTML) 97 Page - Cypress Semiconductor |
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97 / 106 page  PRELIMINARY PSoC® 5: CY8C53 Family Datasheet Document Number: 001-66237 Rev. *A Page 97 of 106 11.9.4 External Crystal Oscillator 11.9.5 External Clock Reference 11.9.6 Phase-Locked Loop Table 11-71. ECO AC Specifications Parameter Description Conditions Min Typ Max Units F Crystal frequency range 4 – 25 MHz Table 11-72. External Clock Reference AC Specifications[39] Parameter Description Conditions Min Typ Max Units External frequency range 0 – 33 MHz Input duty cycle range Measured at VDDIO/2 30 50 70 % Input edge rate VIL to VIH 0.1 – – V/ns Table 11-73. PLL DC Specifications Parameter Description Conditions Min Typ Max Units IDD PLL operating current In = 3 MHz, Out = 67 MHz – 400 – µA In = 3 MHz, Out = 24 MHz – 200 – µA Table 11-74. PLL AC Specifications Parameter Description Conditions Min Typ Max Units Fpllin PLL input frequency[40] 1– 48 MHz PLL intermediate frequency[41] Output of prescaler 1 – 3 MHz Fpllout PLL output frequency[40] 24 – 67 MHz Lock time at startup – – 250 µs Jperiod-rms Jitter (rms)[39] –– 250 ps Notes 39. Based on device characterization (Not production tested). 40. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL. 41. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16. [+] Feedback |
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