www.austriamicrosystems.com/AS8510

Revision 3.4

21 - 46

AS8510

Datasheet - Detailed Descr i p ti on

7.4.3 Standby Mode1 (SBM1)

The low-power Standby Mode can be entered only through the STOP state. Transition to SBM1 mode occurs when the “START BIT” D0 of Mode

Control register MOD_CTL_REG in Table 33 is set to “1” and Mode Control Bits to “10” through SPI. In this mode the date rate is programmable

with the time of Ta. An interrupt signal is generated on INT at the rate of Ta secs., and with a pulse width of eight cycles of lp_clk. The data is

stable up to the next interrupt. The functionality is illustrated in Figure. During the period of Ta, only one data sample is made available and,

during the rest of the period, the device is maintained in STOP state to reduce power consumption. The microcontroller which receives the data

on the Interrupt, is also expected to be processing the data for a short time as shown clearly in the Figure 7 to ensure the overall low-power

consumption of the data acquisition and processing system.

Figure 7. Standby Mode 1

7.4.4 Standby Mode2 (SBM2)

Standby Mode 2 is an extension of the Standby Mode1 to achieve even a lower power in the data acquisition system by providing interrupt to the

microcontroller only when the data sample exceeds the set current threshold. The Standby Mode can be entered only through the STOP state.

Transition to SBM2 mode occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in Table 33 is set to “1” and Mode Control

Bits D7,D6 to “1,1” through SPI. In this mode the date rate is programmable with the time of Ta in the Ta control registers B, C. The data sample

is made available and an interrupt signal is generated on INT pin only when the input signal exceeds the threshold set in Current Threshold

Registers D,E. It should be noted here that the data is stable for Ta secs. The functionality is illustrated in Figure 8.

Figure 8. Standby Mode 2

MCU

ADC

t

T

Start SBM1

sec.

sec.

sec.

V, I, T

T

T

V, I, T

MCU

conv

conv

conv

MCU

INT

Channel

DATA Register

DATA – A1

DATA – A0

DATA – A2

DATA – A3

ADC

t

Start SBM2

I

I

MCU

|I| > I Threshold

INT

Channel

DATA Register

DATA – A1

DATA – A0

DATA – A2

DATA – A3