HT45B0F datasheet(5/23 Pages) HOLTEK

5 / 23 page

HT45B0F

Rev. 1.00

June 7, 2011

Functional Description

The HT45B0F is full-duplex asynchronous serial com-

munications UART interface that enables communica-

tion with external devices that contain a serial interface.

The UART function has many features and can transmit

and receive data serially by transferring a frame of data

with eight or nine data bits per transmission as well as

being able to detect errors when the data is overwritten

or incorrectly framed. All data transmissions and recep-

tions between MCU and HT45B0F including UART

commands are conducted along this interconnected SPI

interface. The UART function control is executed by the

MCU using its SPI Master serial interface. The device

contains its own independent interrupt which can be

used to indicate when a data reception occurs or when a

data transmission has terminated.

SPI Interface

The MCU communicates with the device via an internal

SPI interface. The SPI interface on this device is com-

prised of four signals: SCS (SPI Chip Select), SCK (SPI

Clock), SDI (Serial Data Input) and SDO (Serial Data

Output). The SPI master, which is the MCU, asserts

SCS by pulling it low to start the data transaction cycle.

When the first 8 bits of data are transmitted, SCS should

not return to a high level. Instead, SCS must remain at a

low level until the whole 16-bit data transaction is com-

pleted. If SCS is de-asserted, that is returned to a high

level before the 16-bit data transaction is completed, all

data bits will be discarded by the device SPI slave.

SPI Timing

Both read and write operations are conducted along the

SPI common interface with the following format:

· Write Type Format: 8-bit command input + 8-bit data

input

· Read Type Format: 8-bit command input + 8-bit data

output

To initiate a data transaction, the MCU master SPI

needs to pull SCS to a low level first and then also pull

SCK low. The input data bit on SDI should be stable be-

fore the next SCK rising edge, as the device will latch

the SDI status on the next SCK rising edge. Regarding

the SDO line, the output data bit will be updated on the

SCK falling edge. The master needs to obtain the line

status before the next SCK falling edge.

There are 16 bits of data transmitted and/or received by

the SPI interface for each transaction. Each transaction

consists of a command phase and a data phase. When

SCS is high, the SPI interface is disabled and SDO will

be set to a high impedance state.

After a complete transaction has been implemented,

which requires 16 SCK clock cycles, the master needs

to set SCS to a high level in preparation for the next data

transaction.

For write operations, the device will begin to execute the

command only after it receives a 16-bit serial data se-

quence and when the SCS has been set high again by

the master.

For read operations, the device will begin to execute the

command only after it receives an 8-bit read command

after which it will be ready to output data. If necessary,

the master can de-assert the SCS pin to abort the trans-

action at any time which will cause any data transac-

tions to be abandoned.

S C K

S D I

S D O

V D D

S C S

I N T

C L K I

G N D

S C K

S D O

S D I

C l o c k O u t p u t

S C S

V D D

G N D

M C U

R X

T X

I N T

H T 4 5 B 0 F

V D D

For Example Connection

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