HT45B0F datasheet(16/23 Pages) HOLTEK

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HT45B0F

Rev. 1.00

June 7, 2011

· UART receiver

The UART is capable of receiving word lengths of ei-

ther 8 or 9 bits can be selected by programming the

BNO bit in the UCR1 register. When BNO bit is set, the

word length will be set to 9 bits. In this case the 9th bit,

which is the MSB, will be stored in the RX8 bit in the

UCR1 register. At the receiver core lies the Receiver

Shift Register more commonly known as the RSR.

The data which is received on the RX external input

pin is sent to the data recovery block. The data recov-

ery block operating speed is 16 times that of the baud

rate, while the main receive serial shifter operates at

the baud rate. After the RX pin is sampled for the stop

bit, the received data in RSR is transferred to the re-

ceive data register, if the register is empty. The data

which is received on the external RX input pin is sam-

pled three times by a majority detect circuit to deter-

mine the logic level that has been placed onto the RX

pin. It should be noted that the RSR register, unlike

many other registers, is not directly mapped into the

Data Memory area and as such is not available to the

application program for direct read/write operations.

· Receiving data

When the UART receiver is receiving data, the data is

serially shifted in on the external RX input pin to the

shift register, with the least significant bit LSB first.

The RXR register is a four byte deep FIFO data buffer,

where four bytes can be held in the FIFO while the 5th

byte can continue to be received. Note that the appli-

cation program must ensure that the data is read from

RXR before the 5th byte has been completely shifted

in, otherwise the 5th byte will be discarded and an

overrun error OERR will be subsequently indicated.

The steps to initiate a data transfer can be summa-

rized as follows:

¨ Make the correct selection of the BNO, PRT, PREN

and STOPS bits to define the required word length,

parity type and number of stop bits.

¨ Setup the BRG register to select the desired baud

rate.

¨ Set the RXEN bit to ensure that the UART receiver

is enabled and the RX pin is used as a UART re-

ceiver pin.

At this point the receiver will be enabled which will be-

gin to look for a start bit.

When a character is received, the following sequence

of events will occur:

¨ The RXIF bit in the USR register will be set then

RXR register has data available, at least three more

character can be read.

¨ When the contents of the shift register have been

transferred to the RXR register and if the RIE bit is

set, then an interrupt will be generated.

¨ If during reception, a frame error, noise error, parity

error or an overrun error has been detected, then

the error flags can be set.

The RXIF bit can be cleared using the following soft-

ware sequence:

1. A USR register access

2. A RXR register read execution

· Receiving break

Any break character received by the UART will be

managed as a framing error. The receiver will count

and expect a certain number of bit times as specified

by the values programmed into the BNO and STOPS

bits. If the break is much longer than 13 bit times, the

reception will be considered as complete after the

number of bit times specified by BNO and STOPS.

The RXIF bit is set, FERR is set, zeros are loaded into

the receive data register, interrupts are generated if

appropriate and the RIDLE bit is set. If a long break

signal has been detected and the receiver has re-

ceived a start bit, the data bits and the invalid stop bit,

which sets the FERR flag, the receiver must wait for a

valid stop bit before looking for the next start bit. The

receiver will not make the assumption that the break

condition on the line is the next start bit. A break is re-

garded as a character that contains only zeros with

the FERR flag set. The break character will be loaded

into the buffer and no further data will be received until

stop bits are received. It should be noted that the

RIDLE read only flag will go high when the stop bits

have not yet been received. The reception of a break

character on the UART registers will result in the fol-

lowing:

¨ The framing error flag, FERR, will be set.

¨ The receive data register, RXR, will be cleared.

¨ The OERR, NF, PERR, RIDLE or RXIF flags will

possibly be set.

· Idle status

When the receiver is reading data, which means it will

be in between the detection of a start bit and the read-

ing of a stop bit, the receiver status flag in the USR

a zero value. In between the reception of a stop bit

and the detection of the next start bit, the RIDLE flag

will have a high value, which indicates the receiver is

in an idle condition.

· Receiver interrupt

The read only receive interrupt flag RXIF in the USR

An interrupt is generated if RIE=1, when a word is

transferred from the Receive Shift Register, RSR, to

the Receive Data Register, RXR. An overrun error can

also generate an interrupt if RIE=1.

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