HT45B0F datasheet(14/23 Pages) HOLTEK

14 / 23 page

HT45B0F

Rev. 1.00

June 7, 2011

UART Setup and Control

For data transfer, the UART function utilizes a

non-return-to-zero, more commonly known as NRZ, for-

mat. This is composed of one start bit, eight or nine data

bits and one or two stop bits. Parity is supported by the

UART hardware and can be setup to be even, odd or no

parity. For the most common data format, 8 data bits

along with no parity and one stop bit, denoted as 8, N, 1,

is used as the default setting, which is the setting at

power-on. The number of data bits and stop bits, along

with the parity, are setup by programming the corre-

sponding BNO, PRT, PREN and STOPS bits in the

UCR1 register. The baud rate used to transmit and re-

ceive data is setup using the internal 8-bit baud rate

generator, while the data is transmitted and received

LSB first. Although the transmitter and receiver of the

UART are functionally independent, they both use the

same data format and baud rate. In all cases stop bits

will be used for data transmission.

· Enabling/Disabling the UART

The basic on/off function of the internal UART function

is controlled using the UARTEN bit in the UCR1 regis-

ter. If the UARTEN, TXEN and RXEN bits are set, then

these two UART pins will act as normal TX output pin

and RX input pin respectively. If no data is being trans-

mitted on the TX pin, then it will default to a logic high

value.

Clearing the UARTEN bit will disable the TX and RX

pins and these two pins will be in the state of high im-

pedance. When the UART function is disabled, the

buffer will be reset to an empty condition, at the same

time discarding any remaining residual data. Dis-

abling the UART will also reset the enable control, the

error and status flags with bits TXEN, RXEN, TXBRK,

RXIF, OERR, FERR, PERR and NF being cleared

while bits TIDLE, TXIF and RIDLE will be set. The re-

maining control bits in the UCR1, UCR2 and BRG reg-

isters will remain unaffected. If the UARTEN bit in the

UCR1 register is cleared while the UART is active,

then all pending transmissions and receptions will be

immediately suspended and the UART will be reset to

a condition as defined above. If the UART is then sub-

sequently re-enabled, it will restart again in the same

configuration.

· Data, parity and stop bit selection

The format of the data to be transferred is composed

of various factors such as data bit length, parity on/off,

parity type, address bits and the number of stop bits.

These factors are determined by the setup of various

bits within the UCR1 register. The BNO bit controls the

number of data bits which can be set to either 8 or 9.

The PRT bit controls the choice if odd or even parity.

The PREN bit controls the parity on/off function. The

STOPS bit decides whether one or two stop bits are to

be used. The following table shows various formats

for data transmission. The address detect mode con-

trol bit identifies the frame as an address character.

The number of stop bits, which can be either one or

two, is independent of the data length.

Start

Bit

Data

Bits

Address

Bits

Parity

Bits

Stop

Bit

Example of 8-bit Data Formats

18001

17011

17101

Example of 9-bit Data Formats

19001

18011

18101

Transmitter Receiver Data Format

The following diagram shows the transmit and receive

waveforms for both 8-bit and 9-bit data formats.

S t a r t B i t

B i t 0

B i t 1

B i t 2

B i t 3

B i t 4

B i t 5

B i t 6

B i t 7

S t o p B i t

N e x t

S t a r t

B i t

P a r i t y B i t

8 - B i t D a t a F o r m a t

S t a r t B i t

B i t 0

B i t 1

B i t 2

B i t 3

B i t 4

B i t 5

B i t 6

B i t 7

S t o p B i t

N e x t

S t a r t

B i t

P a r i t y B i t

9 - B i t D a t a F o r m a t

B i t 8

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