71M6521FE-IMSLASHF datasheet(35/107 Pages) MAXIM

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71M6521DE/DH/FE Data Sheet

Rev 2

Page: 35 of 107

Interrupt Priority Level Structure

All interrupt sources are combined in groups, as shown in Table 48:

Group

External interrupt 0

Serial channel 1 interrupt

Timer 0 interrupt

External interrupt 2

External interrupt 1

External interrupt 3

Timer 1 interrupt

External interrupt 4

Serial channel 0 interrupt

External interrupt 5

External interrupt 6

Table 48: Priority Level Groups

Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing

one bit in the special function register IP0 and one in IP1. If requests of the same priority level are received

simultaneously, an internal polling sequence as per Table 52 determines which request is serviced first.

An overview of the interrupt structure is given in Figure 6.

IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that

is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY

and RTC_1SEC, which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable

and flag bits (see Table 47) and these interrupts must be cleared by the MPU software.

Interrupt Priority 0 Register (IP0)

MSB

LSB

WDTS

IP0.5

IP0.4

IP0.3

IP0.2

IP0.1

IP0.0

Table 49: The IP0 Register

Note: WDTS is not used for interrupt controls

Interrupt Priority 1 Register (IP1)

MSB

LSB

IP1.5

IP1.4

IP1.3

IP1.2

IP1.1

IP1.0

Table 50: The IP1 Register:

IP1.x

IP0.x

Priority Level

Level0 (lowest)

Level1

Level2

Level3 (highest)

Table 51: Priority Levels

71M6521FE-IM/F 数据表(PDF) 35 Page - Maxim Integrated Products

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