ADL5240

Rev. 0 | Page 16 of 24

Amplifier Bias

The dc bias for the amplifier in ADL5240 is supplied through

Inductor L1 and is connected to the AMPOUT pin. Three

decoupling capacitors (C3, C4, and C5) are used to prevent

RF signals from propagating onto the dc lines. The dc supply

ranges from 4.75 V to 5.25 V and should be connected to the

VCC test point on the evaluation board.

Digital Step Attenuator Bias

The bias for the DSA is provided through the VDD pin. At least

one decoupling capacitor (C8) is recommended on the VDD

trace. The voltage ranges from 4.75 V to 5.25 V and should be

connected to the VDD test point on the evaluation board. The

DSA is shown to work for dc voltages as low as 2.5 V.

Amplifier RF Input Interface

Pin 15 is the RF input for the amplifier of ADL5240. The

amplifier is internally matched to 50 Ω at the input; therefore,

no external components are required. Only a dc blocking

capacitor (C1) is required.

Amplifier RF Output Interface

Pin 10 is the RF output for the amplifier of ADL5240. The

amplifier is internally matched to 50 Ω at the output; therefore,

no external components are required. Only a dc blocking

capacitor (C2) is required. The bias is provided through this pin

via a choke inductor.

DSA RF Input Interface

Pin 4 is the RF input for the DSA of ADL5240. The input

impedance of the DSA is close to 50 Ω over the entire frequency

range; therefore, no external components are required. Only a

dc blocking capacitor (C6) is required.

DSA RF Output Interface

Pin 21 is the RF output for the DSA of ADL5240. The output

impedance of the DSA is close to 50 Ω over the entire frequency

range; therefore, no external components are required. Only a

dc blocking capacitor (C7) is required.

DSA SPI Interface

The DSA of the ADL5240 can operate in either serial or parallel

mode. Pin 32 (SEL) controls the mode of operation. To select serial

mode, connect SEL to ground; to select parallel mode, connect

SEL to VDD. In parallel mode, Pin 25 to Pin 30 (D6 to D1) are

the data bits, with D6 being the LSB. Connect Pin 31 (D0) to

ground during the parallel mode of operation. In serial mode,

Pin 29 is the latch enable (LE), Pin 30 is the data (DATA), and

Pin 31 is the clock (CLK). Pin 26, Pin 27, and Pin 28 are not used

in serial mode and should be connected to ground. Pin 25 (D6)

should be connected to VDD during the serial mode of operation.

To prevent noise from coupling onto the digital signals, an RC filter

can be used on each data line.