ADL5240

Rev. 0 | Page 17 of 24

SPI TIMING

Table 5 provides details about the timing characteristics for the

SPI signals—namely, the clock (CLK), latch enable (LE), and

data (DATA) signals—and Figure 34 shows the corresponding

SPI timing diagram.

SPI Timing Sequence

Figure 35 is the timing sequence for the SPI function using a 6-bit

operation. The clock can be as fast as 20 MHz. In serial mode,

Register B5 (MSB) is first and Register B0 (LSB) is last.

Table 4. Mode Selection Table

Pin 32 (SEL)

Functionality

Connect to Ground

Serial mode

Connect to Supply

Parallel mode

Table 5. SPI Timing Setup

Parameter

Limit

Unit

Test Conditions/Comments

10

MHz

Data clock frequency

30

ns min

Clock high time

30

ns min

Clock low time

10

ns min

Data to clock setup time

10

ns min

Clock to data hold time

10

ns min

Clock low to LE setup time

30

ns min

LE pulse width

CLK

DATA

LE

B4

B3

B1

MSB

B5

LSB

B0

B2

Figure 34. SPI Timing Diagram (Data Is Loaded MSB First), Serial Mode

B4

B3

B1

MSB

B5

LSB

B0

B2

D0/CLK

D1/DATA

D2/LE

D6

Figure 35. SPI Timing Sequence, Serial Mode