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MICRF219 数据表(PDF) 15 Page - Micrel Semiconductor |
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MICRF219 数据表(HTML) 15 Page - Micrel Semiconductor |
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15 / 23 page ![]() Micrel MICRF219 June 2011 15 M9999-060811 (408) 944-0800 SC (MH Carrier (M n Part Number REFO z) Hz) HIB Part Number Abraco 9.81563 315.0 SA-9.815630-F-10-H-30-30-X ABLS-9.81563MHz-10J4Y 12.15269 90.0 3 SA-12.152690-F-10-H-30-30-X ABLS-12.15269MHz-10J4Y 13.02519 418.0 SA-13.025190-F-10-H-30-30-X ABLS-13.025190MHz-10J4Y 13.52127 433.92 SA-13.521270-F-10-H-30-30-X ABLS-13.521270MHz-10J4Y 4. Crystal requencies and Vendor Part Numbers ata n fo ctly, it is dth o ilar to 7, PW2 is ed for the s found by foun , the ble 5. For 50% (100 Therefore, a bandwidth of 13kHz would be necessary (0.65 / 50µsec). However, if this data am a h ty cycle, ba idt re ul Hz (0 20µsec). This exce the m band e odulator circuit. If one tries to excee the im ba idth, e pu would appear tc r w SEL0 BW t Pulse Maxim Baud 50% ycle Table F Demodulator Bandwidth Selection and D Stream Optimization JP1 and JP2 are the bandwidth selectio demodulator bandwidth. To set it corre necessary to know the shortest pulse wi encoded data sent in the transmitter. Sim example of the data profile in the Figure shorter than PW1, so PW2 should be us demodulator bandwidth calculation which i 0.65/shortest pulse width. After this value is setting should be done according to Ta example, if the pulse period is 100µsec, cycle, the pulse width will be 50µsec (PW = × 50%) / 100). r the f the the d duty µsec stre the had ndw pulse p h requi would eriod wit d wo ed a 20% du d be 32.5k maximu then .65 / width of th dem d max um ndw th lse stre hed o ider. JP1 JP2 (hertz) (µsec) for C SEL1 Demod. Shortes um Rate Duty (Hz) Short Short 1625 400 1250 Open Short 3250 200 2500 Short Open 6500 100 5000 Open Open 13000 50 10000 Table 5. JP1 and JP2 Setting, 433.92MHz Other frequencies will have different demodulator bandwidth limits, which is derived from the reference oscillator frequency. Table 6 and Table 7 shows the limits for the other two most used frequencies. S J SEL1 J De B (h Shortest Pulse (µsec) Maximum Baud Rate for 50% Duty Cycle (Hz) EL0 P1 P2 mod. W ertz) Short Short 1565 416 1204 Open Short 3130 208 2408 Short Open 104 4816 6261 Open Open 12523 52 9633 Table 6. P1 an Setting, 418.0MHz SEL0 SEL1 Demod. (hertz) Shortest Pulse (µsec) Maximum Baud Rate for 50% Duty Cycle (Hz) d JP2 JP1 JP2 BW Short Short 1170 445 1123 Open Short 2350 223 2246 Short Open 4700 111 4493 Open Open 9400 56 8987 Table 7. JP1 and JP2 Setting, 315MHz AGC Capacitor and Data Slicer Threshold Capacitor Selection Capacitors C6 and C4 TH and CAGC capacitors respectively providing a time base reference for the data pattern received. These capacitors are selected according to data profile, pulse duty cycle, dead time between two received data packets, and if the data pattern does has or not have a preamble. See Figure 8 for example of a data profile. are C |
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