Data Sheet

ADL5336

Rev. B | Page 5 of 32

TIMING DIAGRAMS

Figure 2. Write Mode Timing Diagram

Figure 3. Read Mode Timing Diagram

WRITE BIT

LSB + 1

LSB

NOTES

1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A WRITE

OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE 8-BIT WORD IS THEN REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING

EDGES OF THE CLOCK.

CLK

LE

DATA

LSB + 2

MSB – 1

MSB

LSB + 3

MSB – 3

MSB – 2

DC

DC

READ BIT

DC

DC

DC

DC

DC

LSB + 1

LSB

CLK

LE

DATA

SDO

NOTES

1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A READ

OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE 8-BIT WORD IS THEN UPDATED AT THE SDO PIN ON CONSECUTIVE FALLING EDGES

OF THE CLOCK.

LSB + 2

LSB + 3

MSB – 3

MSB – 2

MSB – 1

MSB

DC

DC