Data Sheet

ADL5336

Rev. B | Page 25 of 32

EVALUATION BOARD LAYOUT

An evaluation board is available for testing the ADL5336. The evaluation board schematic is shown in Figure 70. Table 11 provides the

component values and suggestions for modifying the component values for the various modes of operation.

Figure 70. Evaluation Board Schematic

32

31

30

29

28

27

26

25

9

10

11

12

13

14

15

16

1

2

3

4

5

6

7

8

17

18

19

20

21

22

23

24

VPOS

DATA

VCM2

SDO

COM

OPM2

OPP2

VPOS

ENBL

INM1

VPOS

VPOS

MODE

INP1

COM

VCM1

ADL5336

0.1µF

C6

C22

open

C26

0Ω

R12

DIG_VPOS

VPOS

C2

10µF

0.1µF

C7

VCM1

0.1µF

C5

VPOS

VPOS

0.1µF

P5

GAIN1

R1

C12

0.1µF

0Ω

R2

C13

0.1µF

0Ω

P4

GAIN2

C16

0.1µF

open

C27

0Ω

R9

open

C28

0Ω

R11

open

C29

0Ω

R10

C18

VPOS

0.1µF

C25

0.1µF

C17

0.1µF

VCM2

C9

0.1µF

C8

0.1µF

OUTPUT1

open

R14

open

R15

6

4

3

1

2

T2

0.1µF

C21

C4

0.1µF

6

1

T1

2

4

3

0.1µF

C3

6

4

3

1

2

T4

0.1µF

C24

C15

0.1µF

C14

0.1µF

INPUT3

open

R4

open

R3

C11

0.1µF

C23

0.1µF

2

1

0.1µF

C10

3

6

4

INPUT2

T5

20

0.1µF

0.1µF

C19

37.4Ω

R6

37.4Ω

R5

OUTPUT2

R8

24.9Ω

R7

24.9Ω

5

1

4

3

T3

VPOS

P2

VPOS

P3

C1

10µF

L2

33µH

L1

33µH

VPOSD

VPOS

COM

COMD

INPUT1

SDO

DATA

CLK

LE

open

R13

Legend

Net Name

Test Point

SMA Input/Output

Digital ground

Analog ground

Jumper

–

–

–

–

–

–