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ADP1614ACPZ-650-R7 数据表(PDF) 15 Page - Analog Devices |
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ADP1614ACPZ-650-R7 数据表(HTML) 15 Page - Analog Devices |
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15 / 16 page ![]() Data Sheet ADP1614 Rev. 0 | Page 15 of 16 PCB LAYOUT GUIDELINES For high efficiency, good regulation, and stability, a well designed PCB layout is required. Use the following guidelines when designing PCBs (see Figure 25 for a block diagram and Figure 2 for a pin configuration). • Keep the low ESR input capacitor (CIN), which is labeled as C4 in Figure 28, close to VIN and GND. This minimizes noise injected into the part from board parasitic inductance. • Keep the high current path from CIN through the L1 inductor to SW and GND as short as possible. • Keep the high current path from VIN through the inductor (L1), the rectifier (D1), and the output capacitor (COUT), which is labeled as C7 in Figure 28, as short as possible. • Keep high current traces as short and as wide as possible. • Place the feedback resistors as close to FB as possible to prevent noise pickup. Connect the ground of the feedback network directly to an AGND plane that makes a Kelvin connection to the GND pin. • Place the compensation components as close as possible to COMP. Connect the ground of the compensation network directly to an AGND plane that makes a Kelvin connection to the GND pin. • Connect the soft start capacitor (CSS), which is labeled as C1 in Figure 28, as close as possible to the device. Connect the ground of the soft start capacitor to an AGND plane that makes a Kelvin connection to the GND pin. • Connect the current limit set resistor (RCL), which is labeled as R4 in Figure 28, as close as possible to the device. Connect the ground of the CL resistor to an AGND plane that makes a Kelvin connection to the GND pin. • The PCB must be properly designed to conduct the heat away from the package. This is achieved by adding thermal vias to the PCB, which provide a thermal path to the inner or bottom layers. Thermal vias should be placed on the PCB underneath the exposed pad of the LFCSP and in the GND plane around the ADP1614 package to improve thermal performance of the package. Avoid routing high impedance traces from the compensation and feedback resistors near any node connected to SW or near the inductor to prevent radiated noise injection. Figure 28. ADP1614 Recommended Top Layer Layout for Boost Application Figure 29. ADP1614 Recommended Bottom Layer Layout for Boost Application |
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