MMA6525KW datasheet(25/56 Pages) FREESCALE

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Sensor

Freescale Semiconductor, Inc.

MMA65xx

3.7

ΣΔ Converter

A sigma delta converter provides the interface between the transducer and the DSP. The output of the

ΣΔ converter is a data

stream at a nominal frequency of 1 MHz.

Figure 11.

ΣΔ Converter Block Diagram

3.8

Digital Signal Processing Block

A digital signal processing (DSP) block is used to perform signal filtering and compensation operations. A diagram illustrating

the signal processing flow is shown in Figure 12.

Figure 12. Signal Chain Diagram

1-BIT

QUANTIZER

z-1

1 - z-1

z-1

1 - z-1

FIRST

INTEGRATOR

SECOND

INTEGRATOR

CINT1

g-CELL

CBOT

CTOP

ΔC = C

TOP - CBOT

ΣΔ_OUT

V =

±2 × V

REF

ADC

DAC

V =

ΔC x V

X / CINT1

ΣΔ_OUT

To SPI

To ARM_x

To SPI

SINC Filter

Section 3.8.2

Low Pass Filter

Section 3.8.3

Compensation

Section 3.8.6

Interpolation

Section 3.8.7

Offset Cancellation

Section 3.8.4

Offset Cancellation

Output Scaling

Raw Output

Scaling

Arm/PCM Output

Section 3.8.9

Section 3.8.10

Table 26. Signal Chain Characteristics

Description

Sample

Time (

μs)

Data Width

Bits

Over Range

Bits

Effective

Bits

Rounding

Resolution Bits

Typical Block

Latency

Reference

ASD

3.2

μs

Section 3.7

SINC Filter

11.2

μs

Section 3.8.2

Low Pass Filter

8/16

Reference

Section 3.8.3

Compensation

8/16

7.875

μs

Section 3.8.6

Interpolation

4/8

ts / 2

Section 3.8.8

Offset

Cancellation

256

N/A

Section 3.8.4

SPI Output

4/8

—

ts / 2

PCM Output

4/8

—

Section 3.8.11

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