MMA6525KW datasheet(10/56 Pages) FREESCALE

10 / 56 page

Sensor

Freescale Semiconductor, Inc.

MMA65xx

2.7

Dynamic Electrical Characteristics - Supply and SPI

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified

1. Parameters tested 100% at final test.

2. Parameters tested 100% at wafer probe.

3. Parameters verified by characterization

4. (*) Indicates a critical characteristic.

5. Verified by qualification testing.

6. Parameters verified by pass/fail testing in production.

7. Functionality verified 100% via scan. Timing characteristic is directly determined by internal oscillator frequency.

8. N/A

9. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. Response is corrected to 0 Hz response.

10.Low-pass filter cutoff frequencies shown are -3 dB referenced to 0 Hz response.

11.Power supply ripple at frequencies greater than 900 kHz should be minimized to the greatest extent possible.

12.Time from falling edge of CS to ARM_X, ARM_Y output valid

13.N/A

14.Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad.

15.Device characterized at all values of VL & VH. Production test is conducted at all typical voltages (VTYP) unless otherwise noted.

16.Data Path Latency is the signal latency from g-cell to SPI output disregarding filter group delays.

17.Filter characteristics are specified independently, and do not include g-cell frequency response.

18.Electrostatic Deflection Test completed during wafer probe.

19.Verified by Simulation.

20.Acceleration Data Request timing constraint only applies for proper operation of the Arming Function

Characteristic

Symbol

Min

Typ

Max

Units

144

145

146

Power-On Recovery Time (VCC = VCCMIN to first SPI access)

Power-On Recovery Time (Internal POR to first SPI access)

SPI Reset Activation Time (CS high to Reset)

tOP

tSPI_RESET

—

840

300

μs

(3)

(3,7)

(7)

147

148

Internal Oscillator Frequency

Test Frequency - Divided from Internal Oscillator

*fOSC

fOSCTST

7.6

0.95

8.4

1.05

MHz

(7)

(1)

149

Serial Interface Timing (See Figure 7, CMISO ≤ 80pF, RMISO ≥ 10kW)

Clock (SCLK) period (10% of VCC to 10% of VCC)*

tSCLK

120

—

(3)

150

Clock (SCLK) high time (90% of VCC to 90% of VCC)

*tSCLKH

—

(3)

151

Clock (SCLK) low time (10% of VCC to 10% of VCC)

*tSCLKL

—

(3)

152

Clock (SCLK) rise time (10% of VCC to 90% of VCC)

tSCLKR

—15

(19)

153

Clock (SCLK) fall time (90% of VCC to 10% of VCC)

tSCLKF

—15

(19)

154

CS asserted to SCLK high (CS = 10% of VCC to SCLK = 10% of VCC)

tLEAD

—

(3)

155

CS asserted to MISO valid (CS = 10% of VCC to MISO = 10/90% of VCC)

tACCESS

——

(3)

156

Data setup time (MOSI = 10/90% of VCC to SCLK = 10% of VCC)

*tSETUP

—

(3)

157

MOSI Data hold time (SCLK = 90% of VCC to MOSI = 10/90% of VCC)

*tHOLD_IN

—

(3)

158

MISO Data hold time (SCLK = 90% of VCC to MISO = 10/90% of VCC)

*tHOLD_OUT

0—

—

(3)

159

SCLK low to data valid (SCLK = 10% of VCC to MISO = 10/90% of VCC) *tVALID

——

(3)

160

SCLK low to CS high (SCLK = 10% of VCC to CS = 90% of VCC)

*tLAG

—

(3)

161

CS high to MISO disable (CS = 90% of VCC to MISO = Hi Z)

*tDISABLE

——

(3)

162

CS high to CS low (CS = 90% of VCC to CS = 90% of VCC)

*tCSN

526

—

(3)

163

SCLK low to CS low (SCLK = 10% of VCC to CS = 90% of VCC)

*tCLKCS

—

(3)

164

CS high to SCLK high (CS = 90% of VCC to SCLK = 90% of VCC)

tCSCLK

—

(19)

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