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Programmer 数据表(PDF) 6 Page - Cypress Semiconductor |
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Programmer 数据表(HTML) 6 Page - Cypress Semiconductor |
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6 / 15 page ![]() CY25200 Document Number: 38-07633 Rev. *H Page 6 of 15 Spread Percentage (SSCLK1 to SSCLK6 Outputs) The SSCLK frequency is programmed to a percentage value from ±0.25% to ±2.5% for center spread and from –0.5% to –5.0% down spread. The granularity is 0.25%. Modulation Frequency The default modulation frequency is 31.5 kHz. Other modulation frequencies available via the configuration software are 30.1 kHz and 32.9 kHz. Figure 3. Using Clock Select, CLKSEL Control Pin Configuration Pinout Table 4. Using Clock Select, CLKSEL Control Pin Input Frequency (MHz) CLKSEL (Pin 4) SSCLK1 (Pin 7) SSCLK2 (Pin 8) SSCLK3 (Pin 9) SSCLK4 (Pin 12) REFOUT (Pin 14) REFOUT (Pin 15) 14.318 CLKSEL = 0 33.33 33.33 33.33 33.33 14.318 14.318 CLKSEL = 1 66.66 66.66 66.66 66.66 14.318 14.318 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS VSSL SSON 33.33/66.66 MHz 14.318 MHz XOUT VDD CLKSEL AVSS 33.33/66.66 MHz REFOUT(14.318 MHz) REFOUT(14.318MHz) AVDD VDDL 33.33/66.66 MHz 33.33/66.66 MHz [+] Feedback |
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